Abstract: Packaged surface mount (SMT) chips having matched top contacts and bottom contacts are stacked. Chip features are selected to provide the desired connectivity between chip layers with a greater ease of manufacture. In one embodiment, additional spacing and routing layers are optionally provided between layers. In another, chips are differentiated by optionally providing different conductor and/or nonvolatile cell configurations. In yet another, a minority of a substrate's contacts are configured for aligning with a dielectric region of a spacing layer or substrate to create very low capacitance signal paths between stacked chips.

Abstract: The present invention provides for an improved printed circuit board assembly. The connector is straddle mounted to an edge of a printed circuit board with first connector leads configured for abutment with a primary surface of the printed circuit board (PCB) and second connector leads configured for abutment with a secondary surface of the PCB. Holes are provided in the PCB between the first connector leads. The second connector leads are arranged to abut the PCB directly where the holes open on the secondary surface. Solder is deposited on only the primary surface of the PCB directly on the locations where bond formation is desired between the first connector leads and the PCB, that is, on first contact pads. Solder is deposited in the same process on the primary surface, directly above the locations where bond formation is desired between the second connector leads and the PCB, that is, directly above the second contact pads on the other surface of the PCB.