Abstract: Provided is a method for detecting a memory device. First data is written into memory cells connected to first target word lines; second data is written into memory cells connected to second target word lines arranged between the first target word lines; a first voltage adjustment is performed on the memory cells connected to the first target word lines; the second target word lines are alternately turned on and off for a first preset number of times, upon completion of the first voltage adjustment; a second voltage adjustment is performed on the memory cells connected to the first target word lines; the second target word lines are alternately turned on and off for a second preset number of times, upon completion of the second voltage adjustment; and a read operation is performed on the memory cells connected to the first target word lines.

Abstract: Provided are a memory detection method, a computer device and a storage medium. The method includes: initializing all storage units in a storage unit array; determining a plurality of target wordlines, two adjacent target wordlines being provided with a plurality of interfering wordlines therebetween; turning on the target wordlines, and performing a write operation on storage units connected to the target wordlines; performing repeatedly turn-on and turn-off of the interfering wordlines for a plurality of times; and performing a read operation on the storage units connected to the target wordlines. A write operation is performed on the storage units connected to the interfering wordlines by means of forced current sinking.

Abstract: The present application relates to the field of semiconductors, in particular, to the field of Dynamic Random Access Memories (DRAMs), and provides a method and system for detecting a mismatch of a sense amplifier. The method creates a sense amplifier by delaying switch-on of a positive channel-metal-oxide-semiconductor (PMOS) transistor or a negative channel-metal-oxide-semiconductor (NMOS) transistor in the sense amplifier and shortening a row precharge command period (tRP).

Abstract: Provided is a method for detecting a memory device. First data is written into memory cells connected to first target word lines; second data is written into memory cells connected to second target word lines arranged between the first target word lines; a first voltage adjustment is performed on the memory cells connected to the first target word lines; the second target word lines are alternately turned on and off for a first preset number of times, upon completion of the first voltage adjustment; a second voltage adjustment is performed on the memory cells connected to the first target word lines; the second target word lines are alternately turned on and off for a second preset number of times, upon completion of the second voltage adjustment; and a read operation is performed on the memory cells connected to the first target word lines.

Abstract: A method and device for testing a memory and a method for simulated testing include operations as follows. First data is written into a to-be-tested storage unit through a Sense Amplifier (SA), second data different from the first data is written into the storage unit through the SA, and an amplification duration of the SA is shortened during the writing the second data, and data stored in the storage unit is read, and whether the storage unit is abnormal is determined according to the read data.

Abstract: Provided are a sense amplifying circuit and method, and a semiconductor memory. The sense amplifying circuit includes: a transmission circuit, configured to receive a signal to be processed and perform transmission on the signal to be processed to obtain an initial transmission signal; and an amplifying circuit, configured to receive a first control signal and the signal to be processed, and perform amplification on the initial transmission signal according to the first control signal and the signal to be processed to obtain a target transmission signal.

Abstract: A method and device for testing a memory are provided. The method includes the following operations. After activating at least one word line, at least two times of read operations are performed on a to-be-tested memory cell connected to the activated word line. Whether there is a read abnormality in the to-be-tested memory cell is determined according to an output signal obtained after the at least two times of read operations.

Abstract: Provided are a memory detection method, a computer device and a storage medium. The method includes: initializing all storage units in a storage unit array; determining a plurality of target wordlines, two adjacent target wordlines being provided with a plurality of interfering wordlines therebetween; turning on the target wordlines, and performing a write operation on storage units connected to the target wordlines; performing repeatedly turn-on and turn-off of the interfering wordlines for a plurality of times; and performing a read operation on the storage units connected to the target wordlines. A write operation is performed on the storage units connected to the interfering wordlines by means of forced current sinking.

Abstract: The present application relates to the field of semiconductors, in particular, to the field of Dynamic Random Access Memories (DRAMs), and provides a method and system for detecting a mismatch of a sense amplifier. The method creates a sense amplifier by delaying switch-on of a positive channel-metal-oxide-semiconductor (PMOS) transistor or a negative channel-metal-oxide-semiconductor (NMOS) transistor in the sense amplifier and shortening a row precharge command period (tRP).