Abstract: Clock data recovery can be accomplished using a phase path circuit that is configured to receive a data signal and a clock signal. A phase detection circuit detects phase differences between the data signal and a plurality of clock signals and generates a phase adjustment signal based upon a majority voting of the detected phase differences. Speculative calculation circuits generate speculative phase selection signals. Selection circuits select, in response to the phase adjustment signal, from speculative phase selection signals to provide outputs of the phase path circuit.