Abstract: A microprocessor integrator circuit includes split nanocode memories which enables simultaneous execution of an arithmetic operation and an operand fetch for maximizing through-put. The circuit also includes a shared sequencing arithmetic logic unit which handles all microcode sequencing plus memory address sequencing. The circuit also provides nanocode sequencing which enables storage of constants and data in a microcode space which can include an off-chip writable control store. In addition, two level microcode is utilized to enable long routines to be vertically encoded without the overhead of a large number of read only memory outputs.

Abstract: Logic circuitry provides predetermined logic outputs in response to logical combinations of inputs. The circuitry includes a plurality of input devices for receiving logic inputs and capable of assuming conduction states in response to the logic levels of said inputs. At least one output device is connected to two or more input devices. Means having predetermined logic levels is provided connected intermediate the input and output devices for controlling the conduction state of the output devices as a function of the input devices and the predetermined logic levels.

Abstract: A binary to multistate line driver and remote receiver includes a line driver comprising first and second injection logic encoder circuits. The circuits have current injectors and are connected to receive respective first and second binary signals to provide analog outputs at a signal output terminal in response to the input signals. The encoder circuits each have current injectors with substantially similar structural characteristics. The line driver further includes a reference channel circuit connected to a reference terminal to provide a reference to the encoded signals. The reference circuit has a current injector with structural characteristics substantially similar to the encoder circuit current injectors.

Abstract: Integrated injection logic circuits and semiconductor devices employing threshold functions. Multiple-collector input transistors have their collectors connected to the bases of one or more output transistors. The output transistors have different weighted levels of injection current. The switching states of the output transistors are functions of the number of and conduction state of input transistors to which the output transistor are connected and to the weight of the injection current associated with the output transistor.

Abstract: A parallel shifter consists of a plurality of AND gates arranged in a skewed configuration to simulate the partial products of a multiplication of the binary number to be shifted with a second binary number representing 2.sup.N where N is the number of shift steps. Pseudo multiplication may be accomplished merely by ORing the outputs of the AND gates of any given binary weight since only one partial product of that weight will be non-zero. Left or right shift is accomplished by selection of the most significant or least significant half of the product. Rotation is accomplished by merging of the two halves.

Abstract: A 4 .times. 4 multiplier uses four bit threshold logic type adders. The multiplier per se is arranged in a carry save configuration with first level pseudo type carry-look ahead with the highest weight bit of the product being accomplished by a wired OR connection. The four bit adder itself provides two double threshold detectors responsive to logic levels provided by a level shifter which shifts the logical voltage levels produced by a differential amplifier which sums the four inputs of the adder circuit. This provides the sum output; an additional double threshold detector provides the first carry output and a typical threshold AND gate the second carry output.

Abstract: A high speed threshold switching integrated circuit including a transistor and an integrally formed tunnel diode connected in parallel between the base and emitter of the transistor. The heavy doping necessary for the tunnel diode is achieved through the use of ion implantation. A current pulse applied to the emitter-base contact of the integrated circuit causes no collector current to flow until the point at which the rising current pulse exceeds the peak current of the tunnel diode. As the tunnel diode goes into the negative resistance region the transistor is turned on and rapidly pushed into near saturation with a consequent rapidly rising collector current.