Patents by Inventor Tien Chang
Tien Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12006970Abstract: A ball retainer is provided. The ball retainer includes a chain belt, a hook portion, and a recess portion. The chain belt has a first end and a second end. The hook portion is disposed at the first end. The recess portion is disposed at the second end. An outer circumferential side and an inner circumferential side are formed after the hook portion of the ball retainer is snapped into the recess portion. During operation of the ball retainer after the hook portion is snapped into the recess portion, an acting force is applied to the chain belt so that the hook portion is disengaged from the recess portion. During operation of the ball retainer after the acting force disappears, the first end and the second end of the chain belt approach each other so that the hook portion is accordingly snapped into the recess portion.Type: GrantFiled: August 6, 2021Date of Patent: June 11, 2024Assignee: TBI MOTION TECHNOLOGY CO., LTD.Inventors: Ching-Sheng Lee, Tien-Chang Wu
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Patent number: 12006738Abstract: An extension device, including a connecting base and an anti-theft lock assembly, is provided. The connecting base includes a housing, a first moving member, a fixed member, and a second moving member. The fixed member is disposed at one side of the housing and includes a lock hole. The second moving member is movably disposed between the first moving member and the fixed member. The anti-theft lock assembly is detachably disposed at one side of the fixed member opposite to the second moving member. The anti-theft lock assembly is adapted to pass through the lock hole of the fixed member and push against the second moving member, so that the second moving member abuts against the first moving member to stop the first moving member at a buckling position. In addition, an electronic system, including the extension device, is also provided.Type: GrantFiled: September 27, 2021Date of Patent: June 11, 2024Assignee: PEGATRON CORPORATIONInventors: Chun-Fu Chang, I-Tien Hsieh, Hui-Chen Wang
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Publication number: 20240178319Abstract: A semiconductor device includes a substrate, an interfacial layer formed on the semiconductor substrate, and a high-k dielectric layer formed on the interfacial layer. At least one of the high-k dielectric layer and the interfacial layer is doped with: a first dopant species, a second dopant species, and a third dopant species. The first dopant species and the second dopant species form a plurality of first dipole elements having a first polarity. The third dopant species forms a plurality of second dipole elements having a second polarity. A first concentration ratio of the first concentration of the first dopant species to the second concentration of the second dopant species of the p-type transistor is different from a second concentration ratio of the first concentration of the first dopant species to the second concentration of the second dopant species of the n-type transistor.Type: ApplicationFiled: February 2, 2024Publication date: May 30, 2024Inventors: Hsiang-Pi Chang, Yen-Tien Tung, Dawei Heh, Chung-Liang Cheng, I-Ming Chang, Yao-Sheng Huang, Tzer-Min Shen, Huang-Lin Chao
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Patent number: 11996321Abstract: A method includes forming a conductive feature through a first dielectric layer, sequentially forming a second dielectric layer and a third dielectric layer over the first dielectric layer, and etching the third dielectric layer to form an opening. A first width of the opening at a top surface of the third dielectric layer is greater than a second width of the opening at a first interface between the third dielectric layer and the second dielectric layer. The method also includes etching the second dielectric layer until the opening extends to the conductive feature, thereby forming an enlarged opening, and forming a metal material in the enlarged opening. A third width of the enlarged opening at the first interface is equal to or less than a fourth width of the enlarged opening at a second interface between the second dielectric layer and the first dielectric layer.Type: GrantFiled: June 17, 2021Date of Patent: May 28, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Te-Chih Hsiung, Jyun-De Wu, Yi-Chun Chang, Yi-Chen Wang, Yuan-Tien Tu
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Publication number: 20240170230Abstract: A method for prelithiating a soft carbon negative electrode includes the steps of: disposing the soft carbon negative electrode and a lithium metal piece spaced apart from each other with a lithium-containing electrolyte present therebetween; prelithiating the soft carbon negative electrode at a first constant C-rate until a voltage thereof is reduced to a first predetermined voltage not greater than 0.3 V vs. Li/Li+, the first constant C-rate being not greater than 5 C; prelithiating the soft carbon negative electrode at a second constant C-rate until the voltage thereof is reduced to a second predetermined voltage lower than the first predetermined voltage, the second constant C-rate being not greater than 0.2 C and being less than the first constant C-rate; and prelithiating the soft carbon negative electrode at a prelithiation constant voltage which is not greater than the second predetermined voltage, thereby completing prelithiation of the soft carbon negative electrode.Type: ApplicationFiled: January 13, 2023Publication date: May 23, 2024Inventors: Yan-Shi CHEN, Guo-Hsu LU, Chi-Chang HU, Chih-Yu KU, Tien-Yu YI
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Publication number: 20240143173Abstract: A memory module includes a memory array, an interface and a controller. The memory array includes an array of memory cells and is configured as a dual in-line memory module (DIMM). The DIMM includes a plurality of connections that have been repurposed from a standard DIMM pin out configuration to interface operational status of the memory device to a host device. The interface is coupled to the memory array and the plurality of connections of the DIMM to interface the memory array to the host device. The controller is coupled to the memory array and the interface and controls at least one of a refresh operation of the memory array, control an error-correction operation of the memory array, control a memory scrubbing operation of the memory array, and control a wear-level control operation of the array, and the controller to interface with the host device.Type: ApplicationFiled: January 9, 2024Publication date: May 2, 2024Inventors: Mu-Tien CHANG, Dimin NIU, Hongzhong ZHENG, Sun Young LIM, Indong KIM, Jangseok CHOI
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Patent number: 11967622Abstract: Embodiments provide a dielectric inter block disposed in a metallic region of a conductive line or source/drain contact. A first and second conductive structure over the metallic region may extend into the metallic region on either side of the inter block. The inter block can prevent etchant or cleaning solution from contacting an interface between the first conductive structure and the metallic region.Type: GrantFiled: September 3, 2021Date of Patent: April 23, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Te-Chih Hsiung, Jyun-De Wu, Yi-Chen Wang, Yi-Chun Chang, Yuan-Tien Tu
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Publication number: 20240128531Abstract: The present disclosure discloses a method for recycling all types of lithium batteries. First, the lithium battery waste is acid-leached to obtain a solution containing most of metal ions. After filtering, the solution is separated from the remaining solids, and then the obtained solution is subjected to separate precipitation many times. After separately adjusting the pH value of the solution many times, adding precipitants with a high selectivity ratio, and matching with filtration and separation reaction, all ions in the lithium battery waste are sequentially precipitated in forms of iron phosphate (FePO4), aluminum hydroxide (Al(OH)3), manganese oxide (MnO2), dicobalt trioxide (cobalt oxide, Co2O3), nickel hydroxide (Ni(OH)2), and lithium carbonate (Li2CO3).Type: ApplicationFiled: September 24, 2023Publication date: April 18, 2024Applicant: Cleanaway Company LimitedInventors: CHIH-HUANG LAI, HSIN-FANG CHANG, TZU-MIN CHENG, YUNG-FA YANG, TSUNG-TIEN CHEN, ZHENG-YU CHENG, CHI-YUNG CHANG
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Patent number: 11961893Abstract: Improved conductive contacts, methods for forming the same, and semiconductor devices including the same are disclosed. In an embodiment, a semiconductor device includes a first interlayer dielectric (ILD) layer over a transistor structure; a first contact extending through the first ILD layer, the first contact being electrically coupled with a first source/drain region of the transistor structure, a top surface of the first contact being convex, and the top surface of the first contact being disposed below a top surface of the first ILD layer; a second ILD layer over the first ILD layer and the first contact; and a second contact extending through the second ILD layer, the second contact being electrically coupled with the first contact.Type: GrantFiled: June 18, 2021Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Te-Chih Hsiung, Jyun-De Wu, Yi-Chen Wang, Yi-Chun Chang, Yuan-Tien Tu
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Patent number: 11955338Abstract: A method includes providing a substrate having a surface such that a first hard mask layer is formed over the surface and a second hard mask layer is formed over the first hard mask layer, forming a first pattern in the second hard mask layer, where the first pattern includes a first mandrel oriented lengthwise in a first direction and a second mandrel oriented lengthwise in a second direction different from the first direction, and where the first mandrel has a top surface, a first sidewall, and a second sidewall opposite to the first sidewall, and depositing a material towards the first mandrel and the second mandrel such that a layer of the material is formed on the top surface and the first sidewall but not the second sidewall of the first mandrel.Type: GrantFiled: January 30, 2023Date of Patent: April 9, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shih-Chun Huang, Ya-Wen Yeh, Chien-Wen Lai, Wei-Liang Lin, Ya Hui Chang, Yung-Sung Yen, Ru-Gun Liu, Chin-Hsiang Lin, Yu-Tien Shen
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Patent number: 11940922Abstract: A method of processing in-memory commands in a high-bandwidth memory (HBM) system includes sending a function-in-HBM instruction to the HBM by a HBM memory controller of a GPU. A logic component of the HBM receives the FIM instruction and coordinates the instructions execution using the controller, an ALU, and a SRAM located on the logic component.Type: GrantFiled: December 14, 2022Date of Patent: March 26, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Mu-Tien Chang, Krishna T. Malladi, Dimin Niu, Hongzhong Zheng
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Patent number: 11935793Abstract: A method includes forming a source/drain region in a semiconductor fin; after forming the source/drain region, implanting first impurities into the source/drain region; and after implanting the first impurities, implanting second impurities into the source/drain region. The first impurities have a lower formation enthalpy than the second impurities. The method further includes after implanting the second impurities, annealing the source/drain region.Type: GrantFiled: May 29, 2020Date of Patent: March 19, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Chang Lin, Tien-Shun Chang, Chun-Feng Nieh, Huicheng Chang, Yee-Chia Yeo
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Patent number: 11925990Abstract: An indexable center drill structure comprises a holder, an insert, and at least two screws. The screws are locked to at least two screw holes of the holder and at least two positioning holes of the insert. Through cooperation of two positioning posts and two positioning notches of the holder and the insert, the insert is fixed and locked to an insert attachment seat of the holder in a longitudinal direction and in a transverse direction. Thus, the locking strength between the insert and the holder is increased, and the overall structure is simplified.Type: GrantFiled: January 13, 2022Date of Patent: March 12, 2024Inventor: Hsin-Tien Chang
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Publication number: 20240079409Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a first fin structure. The semiconductor device structure includes a first source/drain structure over the first fin structure. The semiconductor device structure includes a first dielectric layer over the first source/drain structure and the substrate. The semiconductor device structure includes a first conductive contact structure in the first dielectric layer and over the first source/drain structure. The semiconductor device structure includes a second dielectric layer over the first dielectric layer and the first conductive contact structure. The semiconductor device structure includes a first conductive via structure passing through the second dielectric layer and connected to the first conductive contact structure. A first width direction of the first conductive contact structure is substantially parallel to a second width direction of the first conductive via structure.Type: ApplicationFiled: November 6, 2023Publication date: March 7, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jyun-De WU, Te-Chih HSIUNG, Yi-Chun CHANG, Yi-Chen WANG, Yuan-Tien TU, Peng WANG, Huan-Just LIN
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Patent number: 11922072Abstract: An apparatus supports single root input/output virtualization (SR-IOV) capable devices. The apparatus includes input/output ports, and SR-IOV capable PCIe devices. Each SR-IOV capable PCIe device has one or more namespaces or controller memory buffers. The SR-IOV capable PCIe device provides one or more physical functions and virtual functions that can access the one or more namespaces or controller memory buffers. A PCIe switch controller communicates with host servers coupled to the input/output ports, and assigns one or more virtual functions to each host device, and enables the host devices to access one or more namespaces or controller memory buffers through the assigned virtual functions.Type: GrantFiled: September 12, 2022Date of Patent: March 5, 2024Assignee: H3 Platform Inc.Inventors: Chin-Hua Chang, Yao-Tien Huang
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Patent number: 11916017Abstract: An integrated circuit includes a plurality of horizontal conducting lines in a first connection layer, a plurality of gate-conductors below the first connection layer, a plurality of terminal-conductors below the first connection layer, and a via-connector directly connecting one of the horizontal conducting lines with one of the gate-conductors or with one of the terminal-conductors. The integrated circuit also includes a plurality of vertical conducting lines in a second connection layer above the first connection layer, and a plurality of pin-connectors for a circuit cell. A first pin-connector is directly connected between a first horizontal conducting line and a first vertical conducting line atop one of the gate-conductors. A second pin-connector is directly connected between a second horizontal conducting line and a second vertical conducting line atop a vertical boundary of the circuit cell.Type: GrantFiled: August 26, 2021Date of Patent: February 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei-Ling Chang, Chih-Liang Chen, Chia-Tien Wu, Guo-Huei Wu
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Publication number: 20240015828Abstract: The present invention provides a wireless communication method of a multi-link device. The wireless communication method includes the steps of: establishing multiple links with an access point, wherein the multiple links have a current link mode; determining performance of a current link mode and at least one candidate link mode, wherein frequency band(s) corresponding to the current link mode and the at least one candidate link mode are not the same; and if the performance of one of the at least one candidate link mode is greater than the performance of the current link mode, switching the link mode of the multiple links, without reconnecting to the access point, so that the one of the at least one candidate link mode serves as the current link mode to communicate with the access point.Type: ApplicationFiled: June 29, 2023Publication date: January 11, 2024Applicant: MEDIATEK INC.Inventors: Li-Tien Chang, Cheng-Yi Chang, Chun-Ting Lin
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Publication number: 20240004547Abstract: A 3D-stacked memory device including: a base die including a plurality of switches to direct data flow and a plurality of arithmetic logic units (ALUs) to compute data; a plurality of memory dies stacked on the base die; and an interface to transfer signals to control the base die.Type: ApplicationFiled: September 15, 2023Publication date: January 4, 2024Inventors: Mu-Tien Chang, Prasun Gera, Dimin Niu, Hongzhong Zheng
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Patent number: 11854924Abstract: A semiconductor device includes a semiconductor die having an active surface, an opposite surface, a vertical sidewall extending between the active surface and the opposite surface, and input/output (I/O) connections disposed on the active surface. A redistribution layer (RDL) is disposed on the active surface of the semiconductor die. A plurality of first connecting elements is disposed on the RDL. A molding compound encapsulates the opposite surface and the vertical sidewall of the semiconductor die. The molding compound also covers the RDL and surrounds the plurality of first connecting elements. An interconnect substrate is mounted on the plurality of first connecting elements and on the molding compound.Type: GrantFiled: October 27, 2021Date of Patent: December 26, 2023Assignee: MEDIATEK INC.Inventors: Tien-Chang Chang, Yan-Liang Ji
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Publication number: 20230336230Abstract: A method for performing beamforming sounding feedback in a system-parameter-aware manner and associated apparatus are provided. The method applicable to a wireless transceiver device within a wireless communications system may include: checking a plurality of system parameters of the wireless communications system to generate a plurality of checking results of the plurality of system parameters, respectively, wherein any checking result among the plurality of checking results indicates a current value of a corresponding system parameter among the plurality of system parameters; modifying a first beamforming feedback matrix according to the plurality of checking results to generate a second beamforming feedback matrix; and sending beamforming sounding feedback information carrying the second beamforming feedback matrix to another device within the wireless communications system, for further processing of the other device.Type: ApplicationFiled: March 13, 2023Publication date: October 19, 2023Applicant: MEDIATEK INC.Inventors: Chun-Ting Lin, Pu-Hsuan Lin, Tsung-Hsuan Wu, Hung-Tao Hsieh, Yi-Cheng Huang, Li-Tien Chang