Patents by Inventor Tien-Chang Chang
Tien-Chang Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11854924Abstract: A semiconductor device includes a semiconductor die having an active surface, an opposite surface, a vertical sidewall extending between the active surface and the opposite surface, and input/output (I/O) connections disposed on the active surface. A redistribution layer (RDL) is disposed on the active surface of the semiconductor die. A plurality of first connecting elements is disposed on the RDL. A molding compound encapsulates the opposite surface and the vertical sidewall of the semiconductor die. The molding compound also covers the RDL and surrounds the plurality of first connecting elements. An interconnect substrate is mounted on the plurality of first connecting elements and on the molding compound.Type: GrantFiled: October 27, 2021Date of Patent: December 26, 2023Assignee: MEDIATEK INC.Inventors: Tien-Chang Chang, Yan-Liang Ji
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Publication number: 20220181228Abstract: A semiconductor device includes a semiconductor die having an active surface, an opposite surface, a vertical sidewall extending between the active surface and the opposite surface, and input/output (I/O) connections disposed on the active surface. A redistribution layer (RDL) is disposed on the active surface of the semiconductor die. A plurality of first connecting elements is disposed on the RDL. A molding compound encapsulates the opposite surface and the vertical sidewall of the semiconductor die. The molding compound also covers the RDL and surrounds the plurality of first connecting elements. An interconnect substrate is mounted on the plurality of first connecting elements and on the molding compound.Type: ApplicationFiled: October 27, 2021Publication date: June 9, 2022Applicant: MEDIATEK INC.Inventors: Tien-Chang Chang, Yan-Liang Ji
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Patent number: 9847294Abstract: The present invention provides a semiconductor device. The semiconductor device comprises: a metal pad and a first specific metal layer routing. The metal pad is positioned on a first metal layer of the semiconductor device. The first specific metal layer routing is formed in a second metal layer and directly under the metal pad, wherein an oxide layer is positioned between the first metal layer and the second metal layer.Type: GrantFiled: February 14, 2017Date of Patent: December 19, 2017Assignee: MEDIATEK INC.Inventors: Chun-Liang Chen, Tien-Chang Chang, Chien-Chih Lin
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Publication number: 20170162505Abstract: The present invention provides a semiconductor device. The semiconductor device comprises: a metal pad and a first specific metal layer routing. The metal pad is positioned on a first metal layer of the semiconductor device. The first specific metal layer routing is formed in a second metal layer and directly under the metal pad, wherein an oxide layer is positioned between the first metal layer and the second metal layer.Type: ApplicationFiled: February 14, 2017Publication date: June 8, 2017Inventors: Chun-Liang Chen, Tien-Chang Chang, Chien-Chih Lin
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Patent number: 9627336Abstract: The present invention provides a semiconductor device. The semiconductor device comprises: a metal pad and a first specific metal layer routing and a second specific metal layer routing. The metal pad is positioned on a first metal layer of the semiconductor device. The first specific metal layer routing and the second specific metal layer routing are formed in a second metal layer of the semiconductor device, wherein the first specific metal layer routing is directly under the metal pad and the second specific metal layer routing is not directly positioned under the metal pad.Type: GrantFiled: August 29, 2016Date of Patent: April 18, 2017Assignee: MEDIATEK INC.Inventors: Chun-Liang Chen, Tien-Chang Chang, Chien-Chih Lin
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Publication number: 20160372431Abstract: The present invention provides a semiconductor device. The semiconductor device comprises: a metal pad and a first specific metal layer routing and a second specific metal layer routing. The metal pad is positioned on a first metal layer of the semiconductor device. The first specific metal layer routing and the second specific metal layer routing are formed in a second metal layer of the semiconductor device, wherein the first specific metal layer routing is directly under the metal pad and the second specific metal layer routing is not directly positioned under the metal pad.Type: ApplicationFiled: August 29, 2016Publication date: December 22, 2016Inventors: Chun-Liang Chen, Tien-Chang Chang, Chien-Chih Lin
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Patent number: 9455226Abstract: The present invention provides a semiconductor device. The semiconductor device comprises: a metal pad and a first specific metal layer routing. The metal pad is positioned on a first metal layer of the semiconductor device. The first specific metal layer routing is formed on a second metal layer of the semiconductor device, and directly under the metal pad.Type: GrantFiled: January 28, 2014Date of Patent: September 27, 2016Assignee: MEDIATEK INC.Inventors: Chun-Liang Chen, Tien-Chang Chang, Chien-Chih Lin
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Publication number: 20150001675Abstract: A semiconductor circuit comprises a first and a second logic circuit, a first and a second decoupling capacitor. The first decoupling capacitor is arranged in a first area around the first logic circuit and the second decoupling capacitor is arranged in a second area around the second logic circuit. Wherein, the first area is larger than the second area, a gate oxide thickness of the first decoupling capacitor is larger than a gate oxide thickness of the second decoupling capacitor, and a distance between the first area and the first logic circuit is shorter than a distance between the second area and the second logic circuit. Further, the first and second decoupling capacitors are designed without trench.Type: ApplicationFiled: September 19, 2014Publication date: January 1, 2015Inventors: Tien-Chang Chang, Ming-Tzong Yang, Tao Cheng, Cheng-Hsing Chien, Hsin-Hsin Hsiao
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Publication number: 20140217601Abstract: The present invention provides a semiconductor device. The semiconductor device comprises: a metal pad and a first specific metal layer routing. The metal pad is positioned on a first metal layer of the semiconductor device. The first specific metal layer routing is formed on a second metal layer of the semiconductor device, and directly under the metal pad.Type: ApplicationFiled: January 28, 2014Publication date: August 7, 2014Applicant: MEDIATEK INC.Inventors: Chun-Liang Chen, Tien-Chang Chang, Chien-Chih Lin
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Patent number: 8766417Abstract: An integrated circuit chip includes a semiconductor substrate; a first interconnection wire having a first portion and a second portion on the semiconductor substrate, wherein the second portion is separated from the first portion; a second interconnection wire situated under the first interconnection wire; a first conductive via electrically coupling the first portion with the second interconnection wire; a conductive layer situated between the first interconnection wire and the second interconnection wire; and a second conductive via electrically coupling the conductive layer with the second portion.Type: GrantFiled: June 3, 2013Date of Patent: July 1, 2014Assignee: Mediatek Inc.Inventors: Chao-Chun Tu, Shih-Hung Lin, Chih-Chien Huang, Tien-Chang Chang
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Publication number: 20140175608Abstract: A method for including decoupling capacitors into a semiconductor circuit having at least a logic circuit therein, includes: arranging a first decoupling capacitor and a second decoupling capacitor into a first area and a second area around the logic circuit respectively, wherein a gate oxide thickness of the first decoupling capacitor is different from a gate oxide thickness of the second decoupling capacitor, and a distance between the first area and the first logic circuit is shorter than a distance between the second area and the second logic circuit.Type: ApplicationFiled: February 25, 2014Publication date: June 26, 2014Applicant: MEDIATEK INC.Inventors: Tien-Chang Chang, Ming-Tzong Yang, Tao Cheng, Cheng-Hsing Chien, Hsin-Hsin Hsiao
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Patent number: 8669619Abstract: A semiconductor device structure includes a substrate having a transistor thereon; a multi-layer contact etching stop layer (CESL) structure covering the transistor, the multi-layer CESL structure comprising a first CESL and a second CESL; and a dielectric layer on the second CESL. The first CESL is made of a material different from that of the second CESL, and the second CESL is made of a material different from that of the dielectric layer.Type: GrantFiled: November 4, 2010Date of Patent: March 11, 2014Assignee: Mediatek Inc.Inventors: Tien-Chang Chang, Jing-Hao Chen, Ming-Tzong Yang
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Patent number: 8587090Abstract: The invention provides a die seal ring structure. The die seal ring structure includes an inner seal ring portion surrounding an integrated circuit region. An outer seal ring portion is surrounded by a scribe line, surrounding the inner seal ring portion, wherein the outer seal ring portion has an outer top metal layer pattern with a first width extending over the inner seal ring portion and connecting to an inner next-to-top metal layer pattern of the inner seal ring portion. A first redistribution pattern is disposed on the outer top metal layer pattern, having a second width which is narrower than the first width. A second redistribution pattern is disposed on the first redistribution pattern. A redistribution passivation layer covers the second redistribution pattern and the inner seal ring portion, wherein the redistribution passivation layer is separated from the scribe line by a second distance.Type: GrantFiled: May 22, 2012Date of Patent: November 19, 2013Assignee: Mediatek Inc.Inventors: Tien-Chang Chang, Yu-Hua Huang
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Publication number: 20130264681Abstract: An integrated circuit chip includes a semiconductor substrate; a first interconnection wire having a first portion and a second portion on the semiconductor substrate, wherein the second portion is separated from the first portion; a second interconnection wire situated under the first interconnection wire; a first conductive via electrically coupling the first portion with the second interconnection wire; a conductive layer situated between the first interconnection wire and the second interconnection wire; and a second conductive via electrically coupling the conductive layer with the second portion.Type: ApplicationFiled: June 3, 2013Publication date: October 10, 2013Inventors: Chao-Chun Tu, Shih-Hung Lin, Chih-Chien Huang, Tien-Chang Chang
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Patent number: 8476745Abstract: An integrated circuit chip includes a semiconductor substrate; a first interconnection wire having a first portion and a second portion on the semiconductor substrate, wherein the second portion is separated from the first portion; a second interconnection wire situated under the first interconnection wire; a first conductive via electrically coupling the first portion with the second interconnection wire; a conductive layer situated between the first interconnection wire and the second interconnection wire; and a second conductive via electrically coupling the conductive layer with the second portion.Type: GrantFiled: May 4, 2009Date of Patent: July 2, 2013Assignee: Mediatek Inc.Inventors: Chao-Chun Tu, Shih-Hung Lin, Chih-Chien Huang, Tien-Chang Chang
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Publication number: 20130026718Abstract: The invention provides a die seal ring structure. The die seal ring structure includes an inner seal ring portion surrounding an integrated circuit region. An outer seal ring portion is surrounded by a scribe line, surrounding the inner seal ring portion, wherein the outer seal ring portion has an outer top metal layer pattern with a first width extending over the inner seal ring portion and connecting to an inner next-to-top metal layer pattern of the inner seal ring portion. A first redistribution pattern is disposed on the outer top metal layer pattern, having a second width which is narrower than the first width. A second redistribution pattern is disposed on the first redistribution pattern. A redistribution passivation layer covers the second redistribution pattern and the inner seal ring portion, wherein the redistribution passivation layer is separated from the scribe line by a second distance.Type: ApplicationFiled: May 22, 2012Publication date: January 31, 2013Applicant: MediaTek Inc.Inventors: Tien-Chang Chang, Yu-Hua Huang
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Patent number: 8242586Abstract: An integrated circuit chip includes an analog and/or RF circuit block and a seal ring structure surrounding the analog and/or RF circuit block. The seal ring structure comprises a continuous outer seal ring and an inner seal ring, wherein the inner seal ring comprises a gap that is situated in front of the analog and/or RF circuit block.Type: GrantFiled: December 31, 2009Date of Patent: August 14, 2012Assignee: Mediatek Inc.Inventors: Tien-Chang Chang, Shi-Bai Chen, Tao Cheng, Yu-Hua Huang
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Patent number: 8212323Abstract: A seal ring structure for an integrated circuit includes a seal ring being disposed along a periphery of the integrated circuit and being divided into at least a first portion and a second portion, wherein the second portion is positioned facing an analog and/or RF circuit block and is different from the first portion in structure. A P+ region is provided in a P substrate and positioned under the second portion. A shallow trench isolation (STI) structure surrounds the P+ region and laterally extends underneath a conductive rampart of the second portion.Type: GrantFiled: August 5, 2010Date of Patent: July 3, 2012Assignee: Mediatek Inc.Inventors: Tung-Hsing Lee, Tien-Chang Chang, Yuan-Hung Chung
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Patent number: 8188578Abstract: A seal ring structure disposed along a periphery of an integrated circuit. The seal ring is divided into at least a first portion and a second portion. The second portion is positioned facing and shielding an analog and/or RF circuit block from a noise. A deep N well is disposed in a P substrate and is positioned under the second portion. The deep N well reduces the substrate noise coupling.Type: GrantFiled: November 19, 2008Date of Patent: May 29, 2012Assignee: Mediatek Inc.Inventors: Tung-Hsing Lee, Tien-Chang Chang, Yuan-Hung Chung
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Publication number: 20120112289Abstract: A semiconductor device structure includes a substrate having a transistor thereon; a multi-layer contact etching stop layer (CESL) structure covering the transistor, the multi-layer CESL structure comprising a first CESL and a second CESL; and a dielectric layer on the second CESL. The first CESL is made of a material different from that of the second CESL, and the second CESL is made of a material different from that of the dielectric layer.Type: ApplicationFiled: November 4, 2010Publication date: May 10, 2012Inventors: Tien-Chang Chang, Jing-Hao Chen, Ming-Tzong Yang