Abstract: A patterning method is provided. A photoresist layer is formed on a target layer. An etching resistance layer is formed on the photoresist layer. The photoresist layer is exposed to light and therefore a photo acid is generated in first regions of the photoresist layer. The photoresist layer is developed to remove second regions of the photoresist layer. It is noted that the etching resistance layer is non-photosensitive but reactive to the generated photo acid.

Abstract: A system and method for modifying an integrated circuit (IC) layout includes performing a correction process, such as an optical proximity correction (OPC) process, only on regions within designated blocks that are defined around respective modified structures. An IC layout can be compared to a modified version of the IC layout to detect modified structures. One or more large blocks can then be defined around respective modified structures. A correction process can then be performed on only the one or more large blocks. Small blocks within respective large blocks can then be extracted from the modified IC layout and merged with the original IC layout to generate a final modified and corrected IC layout.

Abstract: The invention is directed to a method for patterning a material layer. The method comprises steps of providing a material layer. The material layer has a first hard mask layer and a second hard mask layer successively formed thereon. Then, the second hard mask layer is patterned to form a plurality of openings therein. A patterned photoresist layer is formed to cover the second hard mask layer and the patterned photoresist layer exposes a portion of the openings. The first hard mask layer with the patterned photoresist layer and the patterned second hard mask layer together as a mask. Then, the patterned photoresist layer and the patterned second hard mask layer are removed. The material layer is patterned with the patterned first hard mask layer as a mask.

Abstract: A system and method for modifying an integrated circuit (IC) layout includes performing a correction process, such as an optical proximity correction (OPC) process, only on regions within designated blocks that are defined around respective modified structures. An IC layout can be compared to a modified version of the IC layout to detect modified structures. One or more large blocks can then be defined around respective modified structures. A correction process can then be performed on only the one or more large blocks. Small blocks within respective large blocks can then be extracted from the modified IC layout and merged with the original IC layout to generate a final modified and corrected IC layout.

Abstract: The invention is directed to a method for patterning a material layer. The method comprises steps of providing a material layer. The material layer has a first hard mask layer and a second hard mask layer successively formed thereon. Then, the second hard mask layer is patterned to form a plurality of openings therein. A patterned photoresist layer is formed to cover the second hard mask layer and the patterned photoresist layer exposes a portion of the openings. The first hard mask layer with the patterned photoresist layer and the patterned second hard mask layer together as a mask. Then, the patterned photoresist layer and the patterned second hard mask layer are removed. The material layer is patterned with the patterned first hard mask layer as a mask.

Abstract: A semiconductor process is disclosed, wherein before photoresist is coated on a substrate, a chemical is applied to dampen the substrate. Further, the chemical is applied on the substrate while the substrate is kept in a spinning state. In addition, a photoresist coating process is also provided. Wherein, a substrate is spun at a first speed. Then, a chemical is applied to dampen the surface of the spinning substrate. Next, the photoresist is coated on the surface of the substrate. The present invention can prevent defects in the formed photoresist layer during the coating process and therefore enhance the yield of the subsequent semiconductor process.

Abstract: A method of controlling implantation dosages during coding of read-only memory (ROM) devices is disclosed. According to the method, a semi-manufactured ROM device having a plurality of gates with identically designed gate widths is formed, followed by the formation of a first photoresist layer over the semi-manufactured ROM device. The first photoresist layer is selectively exposed to develop a pattern of pre-code openings, with each pre-code opening being positioned over a word line and between two adjacent bit lines intersecting the word line and with the pre-code openings having substantially identical sizes. A second photoresist layer is then formed over the first photoresist layer, followed by selectively exposing the second photoresist layer to develop a pattern of real-code openings therein, with the real-code openings having substantially identical sizes. A tuned dosage of ions is then implanted through intersections of the real-code and pre-code openings to thereby code the ROM device.

Abstract: A method for forming silicide, at least includes following essential steps: provide substrate which is covered with semiconductor structure which has rugged surface; form silicon layer on semiconductor structure; form a metal layer on silicon layer; form capping layer on metal layer; and perform thermal process to form silicide layer by reacting of metal layer and silicon layer, where the thermal stability of capping layer is superior to the thermal stability of silicide layer. The method further perform a pattern process to form numerous conductive lines at least are made of silicide layer. One main characteristic of this invention is to limit agglomeration of silicide by high thermal stable capping layer, such that occurrence of electrical open induced by open of silicide is reduced.

Abstract: A method for forming a metal/dielectric multi-layered interconnect. A conductive layer is formed over a substrate. A protective film is formed over the conductive layer. A first high-density plasma fluorinated silica glass (HDP-FSG) layer is formed over the substrate by performing a HDP chemical vapor deposition with a low bias-voltage power. A second HDP-FSG layer is formed over the first HDP-FSG film by performing a HDP chemical vapor deposition at a higher bias-voltage power. A chemical-mechanical polishing is carried out to planarize the FSG layer. A silicon oxynitride is formed over the FSG layer. A via opening is formed in the FSG layer above the conductive layer. A barrier layer is formed onto the via opening and silicon oxynitride. Tungsten is deposited over the substrate filling the via opening. A tungsten chemical-mechanical polishing is carried out to remove excess tungsten and barrier layer above the silicon oxynitride layer.

Abstract: A method for forming silicide, at least includes following steps: provide substrate which is covered by semiconductor structure with a rugged topography; form silicon layer on semiconductor structure, where topography of silicon layer is similar to rugged topography; etch silicon layer such that topography of silicon layer is smoothed; form metal layer on silicon layer; and perform thermal process such that suicide layer is made from both metal layer and silicon layer, where suicide layer could be used to form numerous silicide lines. The method could be partially modified as following: provide substrate with rugged first surface; etch substrate such that rugged first surface is changed into smoother second surface; form silicon layer on second surface, where topography of silicon layer is similar to topography of second surface; and form metal layer on silicon layer.

Abstract: A method for forming a metal/dielectric multi-layered interconnect. A conductive layer is formed over a substrate. A protective film is formed over the conductive layer. A first high-density plasma fluorinated silica glass (HDP-FSG) layer is formed over the substrate by performing a HDP chemical vapor deposition with a low bias-voltage power. A second HDP-FSG layer is formed over the first HDP-FSG film by performing a HDP chemical vapor deposition at a higher bias-voltage power. A chemical-mechanical polishing is carried out to planarize the FSG layer. A silicon oxynitride is formed over the FSG layer. A via opening is formed in the FSG layer above the conductive layer. A barrier layer is formed onto the via opening and silicon oxynitride. Tungsten is deposited over the substrate filling the via opening. A tungsten chemical-mechanical polishing is carried out to remove excess tungsten and barrier layer above the silicon oxynitride layer.

Abstract: A method of forming a dual damascene structure. A first low-dielectric-constant dielectric layer, an etching stop layer, a second low-dielectric-constant dielectric layer and a silicon oxynitride layer are sequentially formed over a substrate. A dual damascene slot is formed in the first low-dielectric-constant dielectric layer, and a barrier layer that is formed over the exposed surface of the dual damascene slot and the silicon oxynitride layer. Copper is deposited over the substrate filling the dual damascene slot. A copper chemical-mechanical polishing (Cu CMP) is conducted to remove excess copper material using the barrier layer as a polishing stop layer. A Copper/barrier metal CMP is conducted to remove the barrier layer using the silicon oxynitride as an etching stop layer. An ammonia plasma treatment is performed on the exposed silicon oxynitride, barrier layer and copper on the substrate. Finally, a cap layer is formed over the substrate.