Abstract: A latch circuit includes first and second supply nodes having a first voltage value and a second voltage below the first voltage value, first and second input nodes, first and second output nodes, a first switch coupled between the first and second output nodes and turned on and off responsive to first and second clock signal states, first and second transistors coupled between the respective second and first output nodes and the second supply node. A second switch is coupled between a first transistor gate and the first input node, a third switch is coupled between a second transistor gate and the second input node, and each is turned on and off responsive to the first and second states. During the first state, one of the first or second transistors is part of a low resistance path from the first power supply node to the second power supply node.

Abstract: A latch circuit includes a power supply node, first and second input nodes, and first and second output nodes. A first switching device is coupled between the first and second output nodes and is turned on and off in response to respective first and second states of a clock signal. A first transistor has a source coupled with a common node, a drain coupled with the second output node, and a gate directly coupled with the first input node, and a second transistor has a source coupled with the common node, a drain coupled with the first output node, and a gate directly coupled with the second input node. A second switching device is coupled between the common node and the power supply node and is turned on and off in response to the respective second and first states of the clock signal.

Abstract: A memory array includes a plurality of column segments, each column segment including a plurality of columns of memory cells, a plurality of sense amplifiers selectively coupled to each column of the plurality of columns of a corresponding column segment, pluralities of first and second reference cells, and a reference current circuit. The reference current circuit generates a reference current based on a first current generated by a first reference cell programmed to a low logical value and a second current generated by a second reference cell programmed to a high logical value. Each sense amplifier generates a mirror current based on the reference current, and a logical value based on a comparison of the mirror current to a cell current received from a memory cell of a column of the plurality of columns of the corresponding column segment.

Abstract: The disclosure provides a method for delivering an agent to posterior segment of an eye comprising administrating a pharmaceutical composition comprising the agent and mesoporous silica nanoparticles to the eye. An eye drop and a method for treating an ocular disease in a subject in need of such treatment are also provided.

Abstract: A memory array includes a plurality of column segments, each column segment including a plurality of columns of memory cells, a plurality of sense amplifiers selectively coupled to each column of the plurality of columns of a corresponding column segment, pluralities of first and second reference cells, and a reference current circuit. The reference current circuit generates a reference current based on a first current generated by a first reference cell programmed to a low logical value and a second current generated by a second reference cell programmed to a high logical value. Each sense amplifier generates a mirror current based on the reference current, and a logical value based on a comparison of the mirror current to a cell current received from a memory cell of a column of the plurality of columns of the corresponding column segment.

Abstract: A sensing circuit includes a current generating circuit and a sensing circuit. The current generating circuit includes a first portion configured to generate a first mirrored current corresponding to a first reference cell programmed to a low logical value, a second portion configured to generate a second mirrored current corresponding to a second reference cell programmed to a high logical value, and a transistor configured to generate a reference voltage by conducting a first reference current equal to a sum of the first mirrored current and the second mirrored current. The sensing circuit includes a sense amplifier configured to generate an output voltage having a logical value based on a second reference current and a cell current of a memory cell, the second reference current being generated from the reference voltage.

Abstract: The present invention provides a carboxylated nanodiamond-mediated CRISPR-Cas9 delivery system for gene editing comprising nanodiamond (ND) particles as the carriers of CRISPR-Cas9 components designed to introduce the mutation in a given gene for repairing a tissue damage.

Abstract: A clock generation circuit includes: a two-phase clock generation circuit including first and second branches correspondingly configured to generate a first phase clock signal and a second phase clock signal based correspondingly on a non-inverted clock signal and an inverted clock signal, the first and second branches being cross-coupled with each other; an inverter configured to generate the inverted clock signal based on an input clock signal; and a delay circuit which is non-inverter-based and which is configured to generate the non-inverted clock signal based on the input clock signal, the delay circuit having a predetermined delay.

Abstract: A sensing circuit includes a current generating circuit and a sensing circuit. The current generating circuit includes a first portion configured to generate a first mirrored current corresponding to a first reference cell programmed to a low logical value, a second portion configured to generate a second mirrored current corresponding to a second reference cell programmed to a high logical value, and a transistor configured to generate a reference voltage by conducting a first reference current equal to a sum of the first mirrored current and the second mirrored current. The sensing circuit includes a sense amplifier configured to generate an output voltage having a logical value based on a second reference current and a cell current of a memory cell, the second reference current being generated from the reference voltage.

Abstract: A clock generation circuit includes: a two-phase clock generation circuit including first and second branches correspondingly configured to generate a first phase clock signal and a second phase clock signal based correspondingly on a non-inverted clock signal and an inverted clock signal, the first and second branches being cross-coupled with each other; an inverter configured to generate the inverted clock signal based on an input clock signal; and a delay circuit which is non-inverter-based and which is configured to generate the non-inverted clock signal based on the input clock signal, the delay circuit having a predetermined delay.

Abstract: A circuit includes a memory cell that generates a cell current having a cell current value, a first reference cell that generates a first current having a first current value, and a second reference cell that generates a second current having a second current value. A current generating circuit generates a reference current having a reference current value based on the first current value and the second current value, and a sense amplifier sums, at a comparison node, a third current having the cell current value and a fourth current having the reference current value. A buffer outputs a voltage on the comparison node as an output of the sense amplifier.

Abstract: A clock generation circuit includes: a two-phase clock generation circuit configured to generate a first phase clock signal and a second phase clock signal based correspondingly on a non-inverted clock signal and an inverted clock signal; an inverter configured to generate the inverted clock signal based on an input clock signal; and a delay circuit which is non-inverter-based and which is configured to generate the non-inverted clock signal based on the input clock signal, the delay circuit having a predetermined delay sufficient to induce symmetry in the first and second phase clock signals such that durational midpoints of overlapping opposite phases of the first and second phase clock signals are substantially aligned.

Abstract: A clock generation circuit includes: a two-phase clock generation circuit configured to generate a first phase clock signal and a second phase clock signal based correspondingly on a non-inverted clock signal and an inverted clock signal; an inverter configured to generate the inverted clock signal based on an input clock signal; and a delay circuit which is non-inverter-based and which is configured to generate the non-inverted clock signal based on the input clock signal, the delay circuit having a predetermined delay sufficient to induce symmetry in the first and second phase clock signals such that durational midpoints of overlapping opposite phases of the first and second phase clock signals are substantially aligned.

Abstract: A delay line circuit including: a coarse-tuning arrangement, including delay units, the coarse-tuning arrangement being configured to coarsely-tune an input signal by transferring the input signal through a selected number of the delay units and thereby producing a first output signal; and a fine-tuning arrangement configured to receive the first output signal at a beginning of a signal path which includes at least three serially-connected inverters, finely-tune the first output signal along the signal path, and produce a second output signal at an end of the signal path; the fine-tuning arrangement including: a speed control unit which is selectively-connectable, and a switching circuit to selectively connect the speed control unit to the signal path based on a process-corner signal.

Abstract: A clock generation circuit includes: a two-phase clock generation circuit configured to generate a first phase clock signal and a second phase clock signal based correspondingly on a non-inverted clock signal and an inverted clock signal, the first phase clock signal and the second phase clock signal exhibiting non-overlapping logical high states; an inverter configured to generate the inverted clock signal based on an input clock signal; and a delay circuit which is non-inverter-based and which is configured to generate the non-inverted clock signal based on the input clock signal, the delay circuit having a predetermined delay sufficient to cause a difference between a first duration and a second duration within a clock cycle to be less than a predetermined tolerance.

Abstract: In a charge pump circuit, a first circuit is configured to provide a first node with a first first-voltage level or a first second-voltage level. A second circuit is configured to provide a second node with a second first-voltage level or a second second-voltage level. The first node is coupled with a first end of a first capacitive element. The second node is coupled with a first end of a second capacitive element. A first end of a first voltage transfer circuit is configured to receive an input voltage. A second end of the first voltage transfer circuit is coupled with a second end of the first capacitive element and a first end of a second voltage transfer circuit. A second end of the second voltage transfer circuit is coupled with a second end of the second capacitive element, and is configured to provide an output voltage.

Abstract: A circuit includes a memory cell that generates a cell current having a cell current value, a first reference cell that generates a first current having a first current value, and a second reference cell that generates a second current having a second current value. A current generating circuit generates a reference current having a reference current value based on the first current value and the second current value, and a sense amplifier sums, at a comparison node, a third current having the cell current value and a fourth current having the reference current value. A buffer outputs a voltage on the comparison node as an output of the sense amplifier.

Abstract: A delay line circuit including: a coarse-tuning arrangement, including delay units, the coarse-tuning arrangement being configured to coarsely-tune an input signal by transferring the input signal through a selected number of the delay units and thereby producing a first output signal; and a fine-tuning arrangement configured to receive the first output signal at a beginning of a signal path which includes at least three serially-connected inverters, finely-tune the first output signal along the signal path, and produce a second output signal at an end of the signal path; the fine-tuning arrangement including: a speed control unit which is selectively-connectable, and a switching circuit to selectively connect the speed control unit to the signal path based on a process-corner signal.

Abstract: A latch circuit includes a power supply node, first and second input nodes, and first and second output nodes. A first switching device is coupled between the first and second output nodes and is turned on and off in response to respective first and second states of a clock signal. A first transistor has a source coupled with a common node, a drain coupled with the second output node, and a gate directly coupled with the first input node, and a second transistor has a source coupled with the common node, a drain coupled with the first output node, and a gate directly coupled with the second input node. A second switching device is coupled between the common node and the power supply node and is turned on and off in response to the respective second and first states of the clock signal.

Abstract: A circuit includes a current generating circuit and a sense amplifier. The current generating circuit includes a first current mirror that generates a first current having a first current value less than a value of a first cell current through a first reference cell, and based on a ratio of the first cell current to the first current. A second current mirror generates a second current having a second current value less than a value of a second cell current through a second reference cell, and based on a ratio of the second cell current to the second current. The current generating circuit generates a reference current having a reference current value based on the first and second current values. The sense amplifier receives a third current having a third current value and generates a voltage output based on the reference and third current values.