Abstract: A device model parameter generation system, comprises a user module, for obtaining parameter set configurations and measurement data of devices; a parameter extraction module, for performing parameter extractions on the parameter set configurations and the measurement data, to generate a parameter set; a simulation module, for performing simulations according to the parameter set configurations and the measurement data, to generate a simulation results; an analysis module, for determining whether the devices conform to a trend according to the parameter set, to generate a first determination result, and for determining whether the devices conform to a smoothness according to the first determination result and the parameter set, to generate a second determination result; and a device model parameter generation module, for generating a device model parameters according to the second determination result and the parameter set.

Abstract: A separate quantization method of forming a combination of 4-bit and 8-bit data of a neural network is disclosed. When a training data set and a validation data set exist, a calibration manner is used to determine a threshold for activations of each of a plurality of layers of a neural network model, so as to determine how many of the activations to perform 8-bit quantization. In a process of weight quantization, the weights of each layer are allocated to 4-bit weights and 8-bit weights according to a predetermined ratio, so as to make the neural network model have a reduced size and a combination of 4-bit and 8-bit weights.

Abstract: A separate quantization method of forming a combination of 4-bit and 8-bit data of a neural network is disclosed. When a training data set and a validation data set exist, a calibration manner is used to determine a threshold for activations of each of a plurality of layers of a neural network model, so as to determine how many of the activations to perform 8-bit quantization. In a process of weight quantization, the weights of each layer are allocated to 4-bit weights and 8-bit weights according to a predetermined ratio, so as to make the neural network model have a reduced size and a combination of 4-bit and 8-bit weights.

Abstract: An oral dilator includes a first body, a second body, a rotary member, and a positioning member. The first body includes a housing and a first duckbilled element. The second body includes a second duckbilled element corresponding to the first duckbilled element. The rotary member drives the second body to rotate. The positioning member is on the first body and selectively locks or unlocks the relative position between the first duckbilled element and the second duckbilled element when the second duckbilled element is driven to rotate by the rotary member.

Abstract: A trocar set includes a handle portion, a first sleeve, a second sleeve, and a gasbag. The handle portion includes a grip, a connection part, and a first gas valve. The connection part extends from the grip and includes an assembling channel. The first gas valve is connected to the connection part and communicates with the assembling channel. An assembling end of the first sleeve is assembled to the connection portion. A sleeving end of the first sleeve is provided with a first opening. The second sleeve is retractably connected to the sleeving end of the first sleeve. A sleeve wall of the second sleeve is provided with a second opening. The gasbag is connected to an end of the second sleeve away from the sleeving end and corresponds to the second opening. The design of the retractable sleeves is benefit to perform operation.

Abstract: A trocar set includes a handle portion, a first sleeve, a second sleeve, and a gas tight assembly. The handle portion includes a grip, a connection part, and a second gas valve. The connection part extends from the grip and includes an assembling channel. The second gas valve is connected to the connection part and communicates with the assembling channel. An assembling end of the first sleeve is assembled to the connection part. The second sleeve includes a receiving end, wherein the sleeving end is inserted into the receiving end. The gas tight assembly is fixed to the second sleeve and includes a gas tight sleeve and a gas tight ring. The gas tight sleeve encloses the receiving end, and the gas tight ring is pressed by the gas tight sleeve to be tightly attached to the first sleeve.

Abstract: A trocar set includes a handle portion, a first sleeve, a second sleeve, and a gasbag. The handle portion includes a grip, a connection part, and a first gas valve. The connection part extends from the grip and includes an assembling channel. The first gas valve is connected to the connection part and communicates with the assembling channel. An assembling end of the first sleeve is assembled to the connection portion. A sleeving end of the first sleeve is provided with a first opening. The second sleeve is retractably connected to the sleeving end of the first sleeve. A sleeve wall of the second sleeve is provided with a second opening. The gasbag is connected to an end of the second sleeve away from the sleeving end and corresponds to the second opening. The design of the retractable sleeves is benefit to perform operation.

Abstract: A trocar set includes a handle portion, a first sleeve, a second sleeve, and a gasbag. The handle portion includes a grip, a connection part, and a first gas valve. The connection part extends from the grip and includes an assembling channel. The first gas valve is connected to the connection part and communicates with the assembling channel. An assembling end of the first sleeve is assembled to the connection portion. A sleeving end of the first sleeve is provided with a first opening. The second sleeve is retractably connected to the sleeving end of the first sleeve. A sleeve wall of the second sleeve is provided with a second opening. The gasbag is connected to an end of the second sleeve away from the sleeving end and corresponds to the second opening. The design of the retractable sleeves is benefit to perform operation.

Abstract: A trocar set includes a handle portion, a first sleeve, a second sleeve, and a gas tight assembly. The handle portion includes a grip, a connection part, and a second gas valve. The connection part extends from the grip and includes an assembling channel. The second gas valve is connected to the connection part and communicates with the assembling channel. An assembling end of the first sleeve is assembled to the connection part. The second sleeve includes a receiving end, wherein the sleeving end is inserted into the receiving end. The gas tight assembly is fixed to the second sleeve and includes a gas tight sleeve and a gas tight ring. The gas tight sleeve encloses the receiving end, and the gas tight ring is pressed by the gas tight sleeve to be tightly attached to the first sleeve.

Abstract: A trocar set includes a handle portion, a first sleeve, a second sleeve, a gas tight assembly, and a pull band. A connection part of the handle portion extends from a grip and includes an assembling channel. The first sleeve includes an assembling end, a sleeving end, a first outer sleeve wall, and a fastening component. The assembling end is assembled to the assembling channel, and the fastening component is disposed at the sleeving end and contacts the first outer sleeve wall. A sleeving end of the second sleeve is inserted into the receiving end, and the second inner sleeve wall contacts the fastening component. A gas tight sleeve of the gas tight assembly encloses the receiving end and the blocking component. An outer wall of the gas tight sleeve is provided with a plurality of crossing channels. The pulling band crosses the crossing channel.

Abstract: A tag memory and a cache system with automating tag comparison mechanism and a cache method thereof are provided. The tag memory in the cache system includes a memory cell array, sensing amplifiers and a tag comparison circuit. The memory cell array stores cache tags, and outputs row tags of the cache tags according to an index in a memory address. The sensing amplifiers perform signal amplifications on the row tags to serve as comparison tags. The tag comparison circuit performs parallel comparisons between a target tag in the memory address and the row tags. When one of the row tags matches the target tag, the tag comparison circuit outputs a location of the matched row tag to serve as a first column address. The first column address is a column address where the memory address corresponds to a first data memory in the cache system.

Abstract: An oral dilator includes a first body, a second body, a rotary member, and a positioning member. The first body includes a housing and a first duckbilled element. The second body includes a second duckbilled element corresponding to the first duckbilled element. The rotary member drives the second body to rotate. The positioning member is on the first body and selectively locks or unlocks the relative position between the first duckbilled element and the second duckbilled element when the second duckbilled element is driven to rotate by the rotary member.

Abstract: A tag memory and a cache system with automating tag comparison mechanism and a cache method thereof are provided. The tag memory in the cache system includes a memory cell array, sensing amplifiers and a tag comparison circuit. The memory cell array stores cache tags, and outputs row tags of the cache tags according to an index in a memory address. The sensing amplifiers perform signal amplifications on the row tags to serve as comparison tags. The tag comparison circuit performs parallel comparisons between a target tag in the memory address and the row tags. When one of the row tags matches the target tag, the tag comparison circuit outputs a location of the matched row tag to serve as a first column address. The first column address is a column address where the memory address corresponds to a first data memory in the cache system.

Abstract: The present disclosure provides a memory apparatus including a memory cell array, a plurality of sense amplifiers, at least one first comparing circuit, and a plurality of second comparing circuit. The memory cell array includes a plurality of memory cells. Each of the sense amplifier generates a data signal and an inverted data signal according to a bit line signal and an inverted bit line signal. The first comparing circuits compares the data signals of first and second sense amplifiers with a first tag to generate a first comparing result. The second comparing circuits respectively compare a plurality of second tags with the data signals of the sense amplifiers to respectively generate a plurality of second comparing results.

Abstract: A dynamic scaling processor device and processing method thereof, having a timing decoder, a multi-cycle controller, a correction flip-flop. The timing decoder is provided with a plurality of cycles therein, to receive a plurality of instructions, to select corresponding cycles as its predetermined cycles based on type of each instruction, and output the predetermined cycles and its corresponding instructions to the multi-cycle controller. The multi-cycle controller computes results of the instructions based on the predetermined cycles or a single cycle, and outputs them to the correction flip-flop. The error detection flip-flop utilizes a first clock signal and a stalled second clock signal, to sample a same result, and correct the results when outcomes of samplings are different.

Abstract: A multi-core SOC synchronization component comprises a key administration module, a thread schedule unit supporting data synchronization and thread administration, and an expansion unit serving to expand the memory capacity of the key administration module. The key administration module stores, distributes and manages keys. When the key is assigned to a data synchronization process, the key administration module supports the data synchronization process. When the key is assigned to a thread process, the thread schedule unit performs thread administration. The expansion unit is coupled to an external memory and able to expand the memory of the key administration module. When the keys are expanded or the internal memory is insufficient, the keys are stored in the external memory.

Abstract: A method of a fast system call is provided. First, a logical operation to compute a kernel service routine is used. Then the logical operation result is compared with ciphertext from a key register. At least one input for the logical operation is from the relevant information of the required kernel service routine. For example, the start address of the kernel service routine or the content of the start address of the kernel service routine, or combinations thereof. If the logical operation result equals to the ciphertext of the key register, a switch from a user mode to a kernel mode to read the kernel service routine is allowed. Otherwise, the central processing system executes a corresponding exceptional handler routine. Then the operating system terminates the mode switch request and reports an error to the operating system.

Abstract: A non-intrusive debugging framework for parallel software based on a super multi-core framework is composed of a plurality of core clusters. Each of the core clusters includes a plurality of core processors and a debug node. Each of the core processors includes a DCP. The DCPs and the debug node are interconnected via at least one channel to constitute a communication network inside each of the core clusters. The core clusters are interconnected via a ring network. In this way, the memory inside each of the debug nodes constitutes a non-uniform debug memory space for debugging without affecting execution of the parallel program, such that it is applicable to current diversified dynamic debugging methods under the super multi-core system.

Abstract: A hierarchical ring architecture is constructed with on-chip networks. The on-chip network includes two type-0 ring nodes and two type-1 ring nodes. Multiple data transfer is provided in parallel between multiple processor cores or multiple functional units and register banks with a dynamic configuration. A low control complexity, an optimized local bandwidth, an optimized remote node path, a low routing complexity, and a simplified circuit is thus obtained.

Abstract: The present invention uses a swing structure to avoid using a clock period at a non-efficient execution time. The execution time is precisely controlled to enhance a performance of a processor using a low voltage. Thus, synchronization problems in a chip under different environments are solved for high reliability.