Abstract: Method and apparatus for memory device testing at a higher clock rate than the clock rate provided by a memory tester. The method includes providing a memory tester capable of generating a first clock signal characterized by a first clock frequency, and applying the first clock signal to the memory device. The method also includes receiving a command for activating a high-clock-frequency test mode. The method generates a second clock signal in the memory device in response to the first clock signal. The second clock signal is characterized by a second clock frequency which is higher than the first clock frequency. The method then tests the memory device at the second clock frequency. In a specific embodiment, the method is applied to a serial flash memory device. The invention can also be applied to testing and operating other memory devices or systems that include synchronized circuits.

Abstract: Method and apparatus for memory device testing at a higher clock rate than the clock rate provided by a memory tester. The method includes providing a memory tester capable of generating a first clock signal characterized by a first clock frequency, and applying the first clock signal to the memory device. The method also includes receiving a command for activating a high-clock-frequency test mode. The method generates a second clock signal in the memory device in response to the first clock signal. The second clock signal is characterized by a second clock frequency which is higher than the first clock frequency. The method then tests the memory device at the second clock frequency. In a specific embodiment, the method is applied to a serial flash memory device. The invention can also be applied to testing and operating other memory devices or systems that include synchronized circuits.

Abstract: An integrated circuit memory device has an array of non-floating gate non-volatile flash cells arranged in a NOR configuration. The device further has page buffers and control circuits to operate the array in either a NAND mode of operation or a NOR mode of operation. Finally, the array is partitionable by a user into two partitions such that one partition operates only in the NAND mode while the other partition operates only in a NOR mode.

Abstract: An integrated circuit memory device has an array of non-floating gate non-volatile flash cells arranged in a NOR configuration. The device further has page buffers and control circuits to operate the array in either a NAND mode of operation or a NOR mode of operation. Finally, the array is partitionable by a user into two partitions such that one partition operates only in the NAND mode while the other partition operates only in a NOR mode.

Abstract: A nonvolatile semiconductor memory includes a plurality of memory cells arranged in columns and rows, a plurality of word lines, a plurality of bit lines, a plurality of output buffers, and a plurality of page buffers grouped in a plurality of sub-pages. Each page buffer is connected to corresponding bit lines through a first column decoder circuit and connected to one corresponding output buffer through a second column decoder circuit. This construction allows the peripheral control circuits to clock out data stored in page buffers of a first sub-page into output buffers while latching bit line data into page buffers of a second sub-page. Therefore, this architecture is able to perform read and update the page buffer data of different sub-pages simultaneously. Two sets of address registers are used to store the starting and the end address for programming. During programming, only sub-pages located between the starting and end address will be programmed successively.

Abstract: A nonvolatile semiconductor memory includes a plurality of memory cells arranged in columns and rows, a plurality of word lines, a plurality of bit lines, a plurality of output buffers, and a plurality of page buffers grouped in a plurality of sub-pages. Each page buffer is connected to corresponding bit lines through a first column decoder circuit and connected to one corresponding output buffer through a second column decoder circuit. This construction allows the peripheral control circuits to clock out data stored in page buffers of a first sub-page into output buffers while latching bit line data into page buffers of a second sub-page. Therefore, this architecture is able to perform read and update the page buffer data of different sub-pages simultaneously. Two sets of address registers are used to store the starting and the end address for programming. During programming, only sub-pages located between the starting and end address will be programmed successively.

Abstract: An integrated circuit chip suitable for use in either a single chip packaged configuration or a multi-chip packaged configuration is disclosed. The chip has a conventional memory circuit portion and a control circuit portion. In operation as a single chip packaged configuration, the control circuit portion is inactive. In a multi-chip packaged configuration, the control circuit serves to prolong the activation of the currently addressed memory chip, while delaying the activation of the memory chip which is to be addressed in the next memory address cycle.

Abstract: A nonvolatile semiconductor memory includes a plurality of memory cells arranged in columns and rows, a plurality of word lines, a plurality of bit lines, a plurality of output buffers, and a plurality of page buffers grouped in a plurality of sub-pages. Each page buffer is connected to corresponding bit lines through a first column decoder circuit and connected to one corresponding output buffer through a second column decoder circuit. This construction allows the peripheral control circuits to clock out data stored in page buffers of a first sub-page into output buffers while latching bit line data into page buffers of a second sub-page. Therefore, this architecture is able to perform read and update the page buffer data of different sub-pages simultaneously. Two sets of address registers are used to store the starting and the end address for programming. During programming, only sub-pages located between the starting and end address will be programmed successively.

Abstract: A charge pump circuit which generates an output voltage at a selected level, but variations in the current supplied to the charge pump are limited, and variations in the output current generated by the charge pump are limited. The charge pump circuit is coupled to a power supply which has a supply voltage which varies over a specified range. It includes a first charge pump that generates a reference voltage higher than the supply voltage in response to the supply voltage. A circuit, coupled to the first charge pump and responsive to the reference voltage generates a regulated supply voltage. A second charge pump generates a controlled output voltage in response to the regulated supply voltage. The regulated supply voltage is used by pump clock drivers and as a pump reference supply for the second charge pump.

Abstract: A circuit for speeding up the pre-programming of floating gate storage transistors such as FLASH EPROMS, and particularly speeding up the pre-programming of a block or array of floating gate storage transistors includes a controllable voltage source that supplies gate programming potential across the control gate and source of the FLASH EPROM transistor cells to be programmed. A control circuit is provided that controls the voltage source to vary the gate programming potential during a programming interval as a function of time in order to decrease the time required for a given amount of charge movement to program the selected floating gate transistors. The wordline voltages are varied, while the source voltage is held constant. By starting at a lower wordline voltage, and increasing during the programming interval to a high wordline voltage, the programming speed is increased, and the high final turn-on threshold voltage for the programmed floating gate storage transistors is achieved.

Abstract: A circuit for speeding up the pre-programming of floating gate storage transistors such as FLASH EPROMS, and particularly speeding up the pre-programming of a block or array of floating gate storage transistors includes a controllable voltage source that supplies gate programming potential across the control gate and source of the FLASH EPROM transistor cells to be programmed. A control circuit is provided that controls the voltage source to vary the gate programming potential during a programming interval as a function of time in order to decrease the time required for a given amount of charge movement to program the selected floating gate transistors. The wordline voltages are varied, while the source voltage is held constant. By starting at a lower wordline voltage, and increasing during the programming interval to a high wordline voltage, the programming speed is increased, and the high final turn-on threshold voltage for the programmed floating gate storage transistors is achieved.

Abstract: A non-volatile memory device based on an array of floating gate memory cells includes read, erase, program and verify control logic for the array. A status register is coupled with the control logic and stores statistics determined during verify operations concerning at least one of the erase and program operations. For instance, the control logic may include erase verify resources and program verify resources, and the statistics will indicate a number of memory cells which fail erase or program verify. Alternatively, the statistics may indicate whether a threshold number of sequential bytes in the memory fail program verify for a program or erase operation involving a page or sector of data. In addition, defective addresses can be stored. With the status register, the number of program and erase retries for the device can be significantly reduced, allowing application of the device to real time storage systems. Many real time storage problems are fault tolerant.

Abstract: A circuit for speeding up the pre-programming of floating gate storage transistors such as FLASH EPROMS, and particularly speeding up the pre-programming of a block or array of floating gate storage transistors includes a controllable voltage source that supplies gate programming potential across the control gate and source of the FLASH EPROM transistor cells to be programmed. A control circuit is provided that controls the voltage source to vary the gate programming potential during a programming interval as a function of time in order to decrease the time required for a given amount of charge movement to program the selected floating gate transistors. The wordline voltages are varied, while the source voltage is held constant. By starting at a lower wordline voltage, and increasing during the programming interval to a high wordline voltage, the programming speed is increased, and the high final turn-on threshold voltage for the programmed floating gate storage transistors is achieved.

Abstract: An integrated circuit comprises a functional module such as a FLASH memory with automatic program and erase circuits, test circuitry coupled with the functional module which executes a test of the functional module and generates status information as a result of the test, and non-volatile status write circuitry coupled with the test circuitry on the chip. A circuit in the non-volatile status write circuitry is responsive to the test of the functional circuitry to write the status information to the non-volatile memory. A port is provided on the integrated circuit coupled to the non-volatile memory through which the status information stored in the non-volatile memory is accessible in a test read mode to external devices. In a FLASH EPROM embodiment, the IC includes an array of FLASH EPROM memory cells and a port through which data in the array is accessible by external devices. A test set of FLASH EPROM memory cells is provided in the array.

Abstract: Flash EEPROM cell and array designs, and methods for programming the same result in efficient and accurate programming of a flash EEPROM chip. The flash EEPROM chip comprises a memory array including at least M rows and N columns of flash EEPROM cells. M word lines are each coupled to the flash EEPROM cells in one of the M rows of flash EEPROM cells. A plurality of bit lines are each coupled to the flash EEPROM cells in one of the N columns of flash EEPROM cells. A page buffer coupled to the plurality of bit lines supplies input data to N columns of flash EEPROM cells. Write control circuitry supplies programming voltages for programming input data to the flash EEPROM cells in response to the input data stored in the data input buffer. Verify circuitry automatically verifies programming of the page by resetting bits in the page buffer for each cell which passes.

Abstract: A flexible technique for improving yield of manufacturing of high density of memory devices, such as flash EEPROM, involves reconfiguring an integrated circuit memory array having a plurality of sectors selected by an address decoder in response to an N bit field in an address. If defective sectors are detected in the array, it is partitioned to disable defective sectors by configuring a sector decoder to prevent access to the defective sectors while maintaining sequential addressing remaining sectors in the array. The step of partitioning includes configuring the sector decoder to replace a defective sector in one half of the array by another sector in the other half of the array having N-m of the N address bits in common with the defective sector when m is between 1 and N-1.

Abstract: An improved contactless EPROM array, EPROM cell design, and method for fabricating the same is based on a unique drain-source-drain configuration, in which a single source diffusion is shared by two columns of transistors. An elongated first drain diffusion region, an elongated source diffusion region, and an elongated second drain diffusion region, are formed in a semi-conductor substrate along essentially parallel lines. Field oxide regions are grown on opposite sides of the first and second drain diffusion regions. Floating gates and control gate wordlines are formed orthogonal to the drain-source-drain structure to establish two columns of storage cells having a shared source region. The shared source region is coupled through a bottom block select transistor to a virtual ground terminal. Each drain diffusion region is-coupled through a top block select transistor to global bitline.

Abstract: An improved contactless EPROM array, EPROM cell design, and method for fabricating the same is based on a unique drain-source-drain configuration, in which a single source diffusion is shared by two columns of transistors. An elongated first drain diffusion region, an elongated source diffusion region, and an elongated second drain diffusion region, are formed in a semi-conductor substrate along essentially parallel lines. Field oxide regions are grown on opposite sides of the first and second drain diffusion regions. Floating gates and control gate wordlines are formed orthogonal to the drain-source-drain structure to establish two columns of storage cells having a shared source region. The shared source region is coupled through a bottom block select transistor to a virtual ground terminal. Each drain diffusion region is coupled through a top block select transistor to global bitline.

Abstract: An integrated circuit (IC) includes a functional module such as FLASH memory with automatic program and erase circuits, test circuitry coupled with the functional module which executes a test of the functional module and generates status information as a result of the test, and non-volatile status write circuitry coupled with the test circuitry on the chip. A circuit in the non-volatile status write circuitry is responsive to the test of the functional circuitry to write the status information to the non-volatile memory. A port on the integrated circuit is coupled to the non-volatile memory through which the status information stored in the non-volatile memory is accessible in a test read mode to external devices. In a FLASH EPROM embodiment, the IC includes an array of FLASH EPROM memory cells, a test set of FLASH EPROM memory cells, and a port through which data in the array is accessible by external devices.

Abstract: Contactless flash EPROM cell and array designs, and methods for fabricating the same result in dense, segmentable flash EPROM chips. Also, an extended floating gate structure, and method for manufacturing the extended floating gate allow for higher capacitive coupling ratios in flash EPROM circuitry with very small design rules. The floating gates are extended in a symmetrical fashion in a drain-source-drain architecture, so that each pair of columns of cells has a floating gate which is extended in opposite directions from one another. This allows one to take advantage of the space on the cell normally consumed by the isolation regions, to extend the floating gates without increasing the layouts of the cells. Also, an easily scalable design is based on establishing conductive spacers on the sides of floating gate deposition layers which are used for self-alignment of the source and drain.