Abstract: A process for fabricating a trench power semiconductor device is disclosed. A first dielectric layer between the pad oxide layer and the mask oxide layer is formed so as to form a gate with a height higher than the surface of the pad oxide layer after the first dielectric layer is removed. In addition, a sidewall structure is formed at laterals of the gate protruded from the surface of the trench structure. Hence the source structure and the first conductive layer formed at the surface of the gate can be isolated through the sidewall structure. When the trench power semiconductor device is processed at high frequency, the net resistance of the gate can be reduced by the first conductive layer, and thus the electrical properties thereof can be elevated.

Abstract: A method of manufacturing a trench MOSFET with high cell density is disclosed. The method introduces a sidewall oxide spacer for narrowing the opening of the trench structure, thereby decreasing the cell pitch of the memory units. Moreover, the source structure is formed automatically by means of an extra contact silicon etch for preventing the photoresist from lifting during the ion implantation of the prior art. On the other hand, the contact structure is filled with W-plug for overcoming the defect of poor metal step coverage resulted from filling the contact structure with AlSiCu according to the prior art. Thus, the cell density of the device can be increased; and the Rds-on and the power loss of the device can be decreased.

Abstract: The present invention provides a manufacturing process and the structure of an integrated circuit. In one embodiment, one polysilicon layer deposition and one polysilicon layer etching are used to form the gate of a trench device and the polysilicon layer of a planar device simultaneously. The present invention not only has overcome the problem of the electric leakage, but also has the advantages of withstanding a higher voltage, reducing the relevant cost and increasing the yields. The present invention possesses the outstanding technical features in the field of the power device.

Abstract: A method of manufacturing a trench MOSFET with high cell density is disclosed. The method introduces a sidewall oxide spacer for narrowing the opening of the trench structure, thereby decreasing the cell pitch of the memory units. Moreover, the source structure is formed automatically by means of an extra contact silicon etch for preventing the photoresist from lifting during the ion implantation of the prior art. On the other hand, the contact structure is filled with W-plug for overcoming the defect of poor metal step coverage resulted from filling the contact structure with AlSiCu according to the prior art. Thus, the cell density of the device can be increased; and the Rds-on and the power loss of the device can be decreased.

Abstract: The present invention provides a manufacturing process and the structure of an integrated circuit. In one embodiment, one polysilicon layer deposition and one polysilicon layer etching are used to form the gate of a trench device and the polysilicon layer of a planar device simultaneously. The present invention not only has overcome the problem of the electric leakage, but also has the advantages of withstanding a higher voltage, reducing the relevant cost and increasing the yields. The present invention possesses the outstanding technical features in the field of the power device.

Abstract: An object of the invention is to provide a preventive maintenance for effectively removing polymer stacked on a lower electrode within a reaction chamber of etching equipment during the process of dry etching of a silicon oxide layer. First, the lower electrode is preferably set at 0° C., and then the reaction chamber is pre-cleaned preferably 20 times by a pump/purge cleaning manner. After the pre-cleaning, nitrogen or inert gas is supplied into the reaction chamber such that the internal pressure is equal to atmospheric pressure. Subsequently, the reaction chamber is opened preferably for 10 minutes, and the lower electrode is kept at 0° C. during this moment. Afterwards, the surface of the lower electrode is wiped by a piece of clean cloth to peel off the polymer. Finally, the lower electrode is preferably set at 25° C. and is wiped several times by using de-ionized water, isopropanol (IPA), ethanol, a solution of hydrogen peroxide in water, or Cleaner 5060 produced by the 3M corporation.

Abstract: A method of in situ reactive gas plasma treatment is disclosed. The method is capable of removing a residue remained in a metal etching chamber after the metal etching process to improve the yield of the wafer and the particle performance of the metal etching chamber. The method includes the steps of (a) vactuating the metal etching chamber after the metal etching process, (b) introducing a reactive gas to the metal etching chamber, and (c) applying an electromagnetic power to the metal etching chamber for producing a plasma derived from the reactive gas to remove the residue inside the metal etching chamber and/or on the wafer.

Abstract: A method for polysilicon etching with HBr, He and He/O2 as reactive gas source is disclosed. A chamber pressure greater than 30 mTorr is held to achieve high selectivity to polysilicon over silicon oxide. A total flow rate of HBr and He greater than 420 sccm is provided. Under this condition of the total flow rate of HBr and He, the flow rates of HBr and He are respectively held in the range of about 180-280 sccm, and the flow rate of He/O2 is at about 5-10 sccm.

Abstract: A method for preventing corrosion and particulate in a load-lock chamber is disclosed. The load-lock chamber is adjourning with an etching chamber and a wafer transferred module, each time a wafer in the cassette is transferred into the etching chamber for etching by a transfer arm. After that, the etched wafer is withdrawn by the same way to the cassette. The load-lock chamber comprising an outlet of N2-purge tube therein for venting the vacuum in the load-lock chamber to the surrounding. The method comprising at least a step of coupling heating means to the N2-purge tube, or heating N2 gases before injecting into the N2-purge tube so that the temperature of the N2-purge tube will at least not lower than the temperature of an environment within the load-lock chamber.

Abstract: A method of forming a trench power metal-oxide semiconductor (MOS) transistor over a semiconductor substrate is proposed in the present invention. First, a pad oxide layer is formed on said substrate, a masking layer is then formed on the pad oxide layer. Next, the masking layer and the pad oxide layer are defined the trench pattern, and the substrate is etched to form the trench structure. A gate oxide layer is formed on the outer surface of the trench structure. Then, a conducting layer is fill into said trench structure for serving as a gate structure. The doped areas are formed in the substrate to serve as source structures. Next, the sidewall spacers are formed on sidewalls of the masking layer and the pad oxide layer. A field oxide layer is then formed on the conducting layer.