Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a UE. The UE receives, in a first slot and from a base station, a first signal that is a downlink data signal in a first frequency resource allocation. The UE communicates, with the base station, a second signal in a second slot. A configured time gap between the first slot and the second slot is according to a comparison of the first frequency resource allocation and a second frequency resource allocation.

Abstract: A method for performing polar decoding with aid of notation transformation and associated polar decoder are provided. The method includes: transforming input signals from a 2's complement notation to a signed magnitude notation to generate transformed input signals, wherein during the polar decoding, a plurality of first sub-operations and a plurality of second sub-operations are performed to generate decoding results of the transformed input signals; performing a first sign processing to generate a sign result of a first sub-operation within the plurality of first sub-operations; performing a first magnitude processing to generate a magnitude result of the first sub-operation within the plurality of first sub-operations; performing a second sign processing to generate a sign result of a second sub-operation within the plurality of second sub-operations; and performing a second magnitude processing to generate a magnitude result of the second sub-operation within the plurality of second sub-operations.

Abstract: A method for performing polar decoding with aid of notation transformation and associated polar decoder are provided. The method includes: transforming input signals from a 2's complement notation to a signed magnitude notation to generate transformed input signals, wherein during the polar decoding, a plurality of first sub-operations and a plurality of second sub-operations are performed to generate decoding results of the transformed input signals; performing a first sign processing to generate a sign result of a first sub-operation within the plurality of first sub-operations; performing a first magnitude processing to generate a magnitude result of the first sub-operation within the plurality of first sub-operations; performing a second sign processing to generate a sign result of a second sub-operation within the plurality of second sub-operations; and performing a second magnitude processing to generate a magnitude result of the second sub-operation within the plurality of second sub-operations.

Abstract: An apparatus and method for buffering data in a communication system. The apparatus includes a first and a second storage unit. The first storage unit is configured to store first data in a first mode and retrieve the first data in a second mode. The second storage unit is configured to store second data in the second mode and retrieve the second data in the first mode. The apparatus also has a management logic circuit controlling the first and the second storage units to operate between the first and the second modes. In addition, the management logic circuit performs a collision process if a collision has been detected during a collision detection period.

Abstract: An input port for receiving the 16-bit index value is connected to a plurality of combinatorial logic. The plurality of combinatorial logic directly calculates the TKIP Sbox value based on the index and outputs the TKIP Sbox value on an output port. The plurality of combinatorial logic has a first plurality of combinatorial logic connected to a low part of the index value for calculating a TKIP Sbox left value and a second plurality of combinatorial logic connected to a high part of the index value for calculating a TKIP Sbox right value. The TKIP Sbox value is formed by XORing the TKIP Sbox left value and the TKIP Sbox right value.

Abstract: An apparatus and method for buffering data in a communication system. The apparatus includes a first and a second storage unit. The first storage unit is configured to store first data in a first mode and retrieve the first data in a second mode. The second storage unit is configured to store second data in the second mode and retrieve the second data in the first mode. The apparatus also has a management logic circuit controlling the first and the second storage units to operate between the first and the second modes. In addition, the management logic circuit performs a collision process if a collision has been detected during a collision detection period.

Abstract: An output driver for an integrated circuit performs a precharge function before internal data is available, minimizing the access time for such data. Also, the pull up and pull down circuitry used in the precharge function is separate from the output driver, and independent of the level of the data signal to be driven. A sense circuit senses an initial state of the output pad, before the output signal is supplied to the output pad, which indicates whether a voltage level on the output pad is above a threshold or below the threshold. A precharge circuit includes a pull up circuit and a pull down circuit. The pull up circuit is responsive to the initial state indicating that the voltage level on the output is below the threshold, and the pull down circuit is responsive to the initial state indicating that the voltage level on the output is above the threshold. A detector is coupled to the output, and produces a control signal indicating when output is near the threshold.

Abstract: An on chip voltage generation circuit is provided suitable for use on integrated circuits such as flash memory devices with a low power supply voltage (e.g., 2.7 to 3.6 volts). A voltage boost circuit is coupled to the supply voltage input and to a boost signal, which boosts the on-chip voltage at a node on the integrated circuit in response to a transition of the boost signal. The voltage boost circuit has a first mode which in response to the transition boosts the on-chip voltage at a first rate of boosting until a first threshold, and a second mode which in response to the transition boosts the on-chip voltage at a second rate of boosting until a second threshold. The second rate of boosting in the preferred system is slower than the first rate of boosting. A detection circuit is coupled to the node on the integrated circuit which receives the on-chip voltage, and to the voltage boost circuit.

Abstract: An enhanced word line driver circuit suitable for use on integrated circuits such as flash memory devices with voltage boosting includes a load reduction circuit. In response to a boosted voltage, the load reduction circuit decouples a gate capacitance load of deselected enhanced word line drivers from the boost voltage generator. The reduction of capacitive loading decreases power consumption and shortens the voltage boost time of the memory device.