Patents by Inventor Tien Wei
Tien Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11989264Abstract: An automatic generation system of a training image and a method thereof are provided. The disclosure generates a training image and records the target category and the target position. The disclosure adds the target image to the container image as a candidate image, calculates a reliability of the candidate image, and repeatedly executes the process until the reliability of the candidate image meets a threshold condition for generating the training image. The disclosure is able to generate the training images automatically, and the recognition difficulty of the training image is adjustable by the user, so as to be suitable for customized recognition training.Type: GrantFiled: June 2, 2023Date of Patent: May 21, 2024Assignee: DELTA ELECTRONICS, INC.Inventors: Tien-He Chen, Che-Min Chen, Jia-Wei Yan
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Patent number: 11978675Abstract: A semiconductor device includes a gate structure disposed over a channel region, and a source/drain region. The gate structure includes a gate dielectric layer over the channel region, a first work function adjustment layer, over the gate dielectric layer, a first shield layer over the first work function adjustment layer, a first barrier layer, and a metal gate electrode layer. The first work function adjustment layer is made up of n-type work function adjustment layer and includes aluminum. The first shield layer is made of at least one selected from the group consisting of metal, metal nitride, metal carbide, silicide, a layer containing one or more of F, Ga, In, Zr, Mn and Sn, and an aluminum containing layer having a lower aluminum concentration than the first work function adjustment layer.Type: GrantFiled: November 22, 2021Date of Patent: May 7, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chandrashekhar Prakash Savant, Chia-Ming Tsai, Ming-Te Chen, Tien-Wei Yu
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Publication number: 20240145570Abstract: A semiconductor device includes a gate structure disposed over a channel region and a source/drain region. The gate structure includes a gate dielectric layer over the channel region, one or more work function adjustment material layers over the gate dielectric layer, and a metal gate electrode layer over the one or more work function adjustment material layers. The one or more work function adjustment layers includes an aluminum containing layer, and a diffusion barrier layer is disposed at at least one of a bottom portion and a top portion of the aluminum containing layer. The diffusion barrier layer is one or more of a Ti-rich layer, a Ti-doped layer, a Ta-rich layer, a Ta-doped layer and a Si-doped layer.Type: ApplicationFiled: January 9, 2024Publication date: May 2, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shahaji B. MORE, Chandrashekhar Prakash SAVANT, Tien-Wei YU, Chia-Ming TSAI
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Publication number: 20240144428Abstract: An image processing circuit includes a receiving circuit, a transmitting circuit, a first asynchronous handshake circuit, a super resolution scale-up model and a second asynchronous handshake circuit. The receiving circuit is arranged to receive an input image with a first pixel clock frequency. The first asynchronous handshake circuit is arranged to receive the input image from the receiving circuit according to a receiving timing. The super resolution scale-up model is arranged to scale up the input image to generate an output image with a second pixel clock frequency. The second asynchronous handshake circuit is arranged to output the output image to the transmitting circuit according to a transmitting timing to transmit the output image, wherein the first asynchronous handshake circuit, the super resolution scale-up model, and the second asynchronous handshake circuit operate at a clock frequency independent of the first pixel clock frequency and the second pixel clock frequency.Type: ApplicationFiled: June 28, 2023Publication date: May 2, 2024Applicant: Realtek Semiconductor Corp.Inventors: Tien-Hung Lin, Chia-Wei Yu, Yi-Ting Bao
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Publication number: 20240114487Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a UE. The UE receives, in a first slot and from a base station, a first signal that is a downlink data signal in a first frequency resource allocation. The UE communicates, with the base station, a second signal in a second slot. A configured time gap between the first slot and the second slot is according to a comparison of the first frequency resource allocation and a second frequency resource allocation.Type: ApplicationFiled: September 19, 2023Publication date: April 4, 2024Inventors: Chiou-Wei TSAI, Wei-De WU, Yi-Chia LO, Tien-Shin HO
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Publication number: 20240112360Abstract: A measurement system includes a camera and a processor. The camera is configured to capture a measurement card image of a measurement card, and the measurement card image includes a number of feature pattern images. The processor is electrically connected to the camera and configured for analyzing the feature pattern images to obtain a feature point coordinate of a feature point of each feature pattern image, and inputting the feature point coordinates into a conversion matrix to obtain a tip coordinate of a tip of the measurement card.Type: ApplicationFiled: January 18, 2023Publication date: April 4, 2024Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yu-Wei CHANG, Shih-Fang YANG MAO, Tien-Yan MA
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Publication number: 20240097009Abstract: A semiconductor structure includes a substrate, a channel region, a gate structure, and source/drain regions. The channel region is over the substrate. The gate structure is over the channel region, and includes a high-k dielectric layer, a tungsten layer over the high-k dielectric layer, and a fluorine-containing work function layer over the tungsten layer. The source/drain regions are at opposite sides of the channel region.Type: ApplicationFiled: November 28, 2023Publication date: March 21, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chandrashekhar P. SAVANT, Tien-Wei YU, Ke-Chih LIU, Chia-Ming TSAI
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Publication number: 20240096818Abstract: Devices and method for forming a shielding assembly including a first chip package structure sensitive to magnetic interference (MI), a second chip package structure sensitive to electromagnetic interference (EMI), and a shield surrounding sidewalls and top surfaces of the first chip package structure and the second chip package structure, in which the shield is a magnetic shielding material. In some embodiments, the shield may include silicon steel, in some embodiments, the shield may include Mu-metal. The silicon-steel-based or Mu-metal-based shield may provide both EMI and MI protection to multiple chip package structures with various susceptibilities to EMI and MI.Type: ApplicationFiled: April 20, 2023Publication date: March 21, 2024Inventors: Harry-Hak-Lay Chuang, Yuan-Jen Lee, Kuo-An Liu, Ching-Huang Wang, C.T. Kuo, Tien-Wei Chiang
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Patent number: 11930645Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate, a transistor region, a first and a second contact plug, a first metal via, a magnetic tunneling junction (MTJ) structure, and a metal interconnect. The transistor region includes a gate over the substrate, and a first and a second doped regions at least partially in the substrate. The first and the second contact plug are over the transistor region. The first and the second contact plug include a coplanar upper surface. The first metal via and the MTJ structure are over the first and the second contact plug, respectively. The first metal via is leveled with the MTJ structure. The metal interconnect is over the first metal via and the MTJ structure, and the metal interconnect includes at least two second metal vias in contact with the first metal via and the MTJ structure, respectively.Type: GrantFiled: March 5, 2023Date of Patent: March 12, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Alexander Kalnitsky, Harry-Hak-Lay Chuang, Sheng-Haung Huang, Tien-Wei Chiang
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Patent number: 11908915Abstract: A semiconductor device includes a gate structure disposed over a channel region and a source/drain region. The gate structure includes a gate dielectric layer over the channel region, one or more work function adjustment material layers over the gate dielectric layer, and a metal gate electrode layer over the one or more work function adjustment material layers. The one or more work function adjustment layers includes an aluminum containing layer, and a diffusion barrier layer is disposed at at least one of a bottom portion and a top portion of the aluminum containing layer. The diffusion barrier layer is one or more of a Ti-rich layer, a Ti-doped layer, a Ta-rich layer, a Ta-doped layer and a Si-doped layer.Type: GrantFiled: May 23, 2022Date of Patent: February 20, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shahaji B. More, Chandrashekhar Prakash Savant, Tien-Wei Yu, Chia-Ming Tsai
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Publication number: 20240057344Abstract: A semiconductor device includes a bottom electrode via, a top electrode via over the bottom electrode via, a memory cell between the bottom electrode via and the top electrode via, a first dielectric layer over the memory cell, and a second dielectric layer over the first dielectric layer, and a via structure separated from the memory cell. A height of the via structure is substantially equal to a sum of a height of the bottom electrode via, a height of the memory cell, and a height of the top electrode via. The first dielectric layer partially surrounds a first portion of the via structure, and the second dielectric layer partially surrounds a second portion of the via structure. A height of the second portion of the via structure is greater than a height of the first portion of the via structure.Type: ApplicationFiled: October 24, 2023Publication date: February 15, 2024Inventors: HARRY-HAK-LAY CHUANG, WU-CHANG TSAI, TIEN-WEI CHIANG
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Patent number: 11855189Abstract: A semiconductor device includes a substrate, a semiconductor fin, a gate structure, and source/drain structures. The semiconductor fin extends upwardly from the substrate. The gate structure is across the semiconductor fin and includes a high-k dielectric layer over the semiconductor fin, a fluorine-containing work function layer over the high-k dielectric layer and comprising fluorine, a tungsten-containing layer over the fluorine-containing work function layer, and a metal gate electrode over the tungsten-containing layer. The source/drain structures are on the semiconductor fin and at opposite sides of the gate structure.Type: GrantFiled: June 17, 2022Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chandrashekhar P. Savant, Tien-Wei Yu, Ke-Chih Liu, Chia-Ming Tsai
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Patent number: 11832452Abstract: A semiconductor device includes a first dielectric layer, a second dielectric layer and a memory device. The second dielectric layer includes a first layer and a second layer. The memory device includes a first conductive structure under the first dielectric layer, a second conductive structure over the second dielectric layer, and a memory cell between the first and the second dielectric layers. The memory cell includes a bottom electrode via, a bottom electrode over the bottom electrode via, a top electrode over the bottom electrode, a top electrode via over the top electrode, and a MTJ between the top electrode and the bottom electrode. The second layer of the second dielectric layer surrounds sidewalls of the top electrode via entirely. The first layer of the second dielectric layer surrounds sidewalls of the bottom electrode entirely, sidewalls of the MTJ entirely, and sidewalls of the top electrode entirely.Type: GrantFiled: July 30, 2021Date of Patent: November 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Harry-Hak-Lay Chuang, Wu-Chang Tsai, Tien-Wei Chiang
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Publication number: 20230377994Abstract: A semiconductor device includes a gate structure disposed over a channel region, and a source/drain region. The gate structure includes a gate dielectric layer over the channel region, a first work function adjustment layer, over the gate dielectric layer, a first shield layer over the first work function adjustment layer, a first barrier layer, and a metal gate electrode layer. The first work function adjustment layer is made up of n-type work function adjustment layer and includes aluminum. The first shield layer is made of at least one selected from the group consisting of metal, metal nitride, metal carbide, silicide, a layer containing one or more of F, Ga, In, Zr, Mn and Sn, and an aluminum containing layer having a lower aluminum concentration than the first work function adjustment layer.Type: ApplicationFiled: August 3, 2023Publication date: November 23, 2023Inventors: Chandrashekhar Prakash SAVANT, Chia-Ming Tsai, Ming-Te Chen, Tien-Wei Yu
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Publication number: 20230371277Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a plurality of doped regions located in a substrate; a first dielectric layer located on the substrate; a plurality of first contacts and second contacts located in the first dielectric layer and connected to the plurality of doped regions; a second dielectric layer located on the first dielectric layer; a memory element located in the second dielectric layer, the memory element being electrically connected to the second contact; and a plurality of conductive interconnects located in the second dielectric layer. The conductive interconnects being electrically connected to the plurality of first contacts, and a top surface of the conductive interconnects being at a same level as a top surface of the memory element. A method of fabricating a semiconductor device, and a semiconductor structure having a semiconductor device are also provided.Type: ApplicationFiled: July 11, 2023Publication date: November 16, 2023Inventors: ALEXANDER KALNITSKY, HARRY-HAK-LAY CHUANG, SHENG-HAUNG HUANG, TIEN-WEI CHIANG
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Publication number: 20230361050Abstract: A package structure includes a mounting pad having a mounting surface; a semiconductor chip having a magnetic device, a first magnetic field shielding, and a molding. The semiconductor chip comprises a first surface perpendicular to a thickness direction of the semiconductor chip, a second surface opposite to the first surface, wherein the second surface is attached to the mounting surface of the mounting pad, and a third surface connecting the first surface and the second surface. The first magnetic field shielding including a plurality of segments laterally at least partially surrounding the semiconductor chip, wherein a bottom surface of the first magnetic field shielding is attached to the mounting surface of the mounting pad, wherein the mounting surface comprises first portion free from overlapping with the first magnetic field shielding from a top view perspective. The molding surrounding the mounting pad and in direct contact with the mounting surface.Type: ApplicationFiled: July 18, 2023Publication date: November 9, 2023Inventors: HARRY-HAK-LAY CHUANG, CHIA-HSIANG CHEN, MENG-CHUN SHIH, CHING-HUANG WANG, TIEN-WEI CHIANG
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Publication number: 20230333157Abstract: In some embodiments, a semiconductor wafer testing system is provided. The semiconductor wafer testing system includes a semiconductor wafer prober having one or more conductive probes, where the semiconductor wafer prober is configured to position the one or more conductive probes on an integrated chip (IC) that is disposed on a semiconductor wafer. The semiconductor wafer testing system also includes a ferromagnetic wafer chuck, where the ferromagnetic wafer chuck is configured to hold the semiconductor wafer while the wafer prober positions the one or more conductive probes on the IC. An upper magnet is disposed over the ferromagnetic wafer chuck, where the upper magnet is configured to generate an external magnetic field between the upper magnet and the ferromagnetic wafer chuck, and where the ferromagnetic wafer chuck amplifies the external magnetic field such that the external magnetic field passes through the IC with an amplified magnetic field strength.Type: ApplicationFiled: June 20, 2023Publication date: October 19, 2023Inventors: Harry-Hak-Lay Chuang, Chih-Yang Chang, Ching-Huang Wang, Tien-Wei Chiang, Meng-Chun Shih, Chia Yu Wang
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Patent number: 11784187Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region made of a semiconductor material, a first work function adjustment material layer is formed over the gate dielectric layer, an adhesion enhancement layer is formed on the first work function adjustment material layer, a mask layer including an antireflective organic material layer is formed on the adhesion enhancement layer, and the adhesion enhancement layer and the first work function adjustment material layer are patterned by using the mask layer as an etching mask. The adhesion enhancement layer has a higher adhesion strength to the antireflective organic material layer than the first work function adjustment material layer.Type: GrantFiled: July 21, 2020Date of Patent: October 10, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shahaji B. More, Chandrashekhar Prakash Savant, Tien-Wei Yu, Chia-Ming Tsai
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Publication number: 20230317629Abstract: In some embodiments, the present application provides an integrated chip. The integrated chip includes a chip comprising a semiconductor device. A shielding structure abuts the chip. The shielding structure comprises a first horizontal region adjacent to a first horizontal surface of the chip. The first horizontal region comprises a first multilayer structure comprising a first dielectric layer and two or more metal layers. The first dielectric layer is disposed between the two or more metal layers.Type: ApplicationFiled: June 9, 2023Publication date: October 5, 2023Inventors: Harry-Hak-Lay Chuang, Tien-Wei Chiang, Kuo-An Liu, Chia-Hsiang Chen
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Patent number: 11749617Abstract: The present disclosure provides a package structure, including a mounting pad having a mounting surface, a semiconductor chip disposed on the mounting surface of the mounting pad, wherein the semiconductor chip includes a first surface, a second surface opposite to the first surface and facing the mounting surface, and a third surface connecting the first surface and the second surface, a first magnetic field shielding, including a first portion proximal to the third surface of the semiconductor chip, wherein the first portion has a first height calculated from the mounting surface to a top surface, and a second portion distal to the semiconductor chip, has a second height calculated from the mounting surface to a position at a surface facing away from the mounting surface, wherein the second height is less than the first height, wherein the second portion has an inclined sidewall.Type: GrantFiled: June 30, 2022Date of Patent: September 5, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Harry-Hak-Lay Chuang, Chia-Hsiang Chen, Meng-Chun Shih, Ching-Huang Wang, Tien-Wei Chiang