Patents by Inventor Tien Yu T. Lee
Tien Yu T. Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8530346Abstract: An electronic device can include an interconnect level including a bonding pad region. An insulating layer can overlie the interconnect level and include an opening over the bonding pad region. In one embodiment, a conductive stud can lie within the opening and can be substantially encapsulated. In another embodiment, the electronic device can include a barrier layer lying along a side and a bottom of the opening and a conductive stud lying within the opening. The conductive stud can substantially fill the opening. A majority of the conductive stud can lie within the opening. In still another embodiment, a process for forming an electronic device can include forming a conductive stud within the opening wherein from a top view, the conductive stud lies substantially completely within the opening. The process can also include forming a second barrier layer overlying the conductive stud.Type: GrantFiled: October 11, 2010Date of Patent: September 10, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Lakshmi N. Ramanathan, Tien Yu T. Lee, Jinbang Tang
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Publication number: 20120252169Abstract: An integrated circuit assembly includes a panel including an semiconductor device at least partially surrounded by an encapsulant. A panel upper surface and a device active surface are substantially coplanar. The assembly further includes one or more interconnect layers overlying the panel upper surface. Each of the interconnect layers includes an insulating film having contacts formed therein an interconnect metallization formed thereon. A lower surface of the panel is substantially coplanar with either a backside of the device or a lower surface of a thermally and electrically conductive slab that has an upper surface in thermal contact with the device backside. The assembly may also include a set of panel vias. The panel vias are thermally and electrically conductive conduits extending through the panel between the interconnect layer and suitable for bonding with a land grid array (LGA) or other contact structure of an underlying circuit board.Type: ApplicationFiled: June 14, 2012Publication date: October 4, 2012Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Neil T. Tracht, Darrel R. Frear, James R. Griffiths, Lizabeth Ann A. Keser, Tien Yu T. Lee, Elie A. Maalouf
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Patent number: 8217511Abstract: An integrated circuit assembly includes a panel including an semiconductor device at least partially surrounded by an encapsulant. A panel upper surface and a device active surface are substantially coplanar. The assembly further includes one or more interconnect layers overlying the panel upper surface. Each of the interconnect layers includes an insulating film having contacts formed therein an interconnect metallization formed thereon. A lower surface of the panel is substantially coplanar with either a backside of the device or a lower surface of a thermally and electrically conductive slab that has an upper surface in thermal contact with the device backside. The assembly may also include a set of panel vias. The panel vias are thermally and electrically conductive conduits extending through the panel between the interconnect layer and suitable for bonding with a land grid array (LGA) or other contact structure of an underlying circuit board.Type: GrantFiled: July 31, 2007Date of Patent: July 10, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Neil T. Tracht, Darrel R Frear, James R. Griffiths, Lizabeth Ann A. Keser, Tien Yu T. Lee, Elie A. Maalouf
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Patent number: 7892882Abstract: A package assembly 200 includes a semiconductor die (e.g., an RF power amplifier) 208 fixed within the cavity of a conductive leadframe 204 using a thermally and electrically-conductive adhesive material 209. The semiconductor die 209 has a first side and a second side, wherein the first side includes at least one active area, and the second side includes at least one contact region. The conductive leadframe (e.g., a copper leadframe) 204 has two planar surfaces and a cavity formed therein. The adhesive material 209 is configured to couple the semiconductor die 208 within the cavity of the conductive leadframe 204 such that the first side of the semiconductor die is substantially coplanar with the first surface of the conductive leadframe.Type: GrantFiled: June 9, 2006Date of Patent: February 22, 2011Assignee: Freescale Semiconductor, Inc.Inventors: George R. Leal, Victor A. Chiriac, Tien Yu T. Lee, Marc A. Mangrum, Robert J. Wenzel
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Publication number: 20110027984Abstract: An electronic device can include an interconnect level including a bonding pad region. An insulating layer can overlie the interconnect level and include an opening over the bonding pad region. In one embodiment, a conductive stud can lie within the opening and can be substantially encapsulated. In another embodiment, the electronic device can include a barrier layer lying along a side and a bottom of the opening and a conductive stud lying within the opening. The conductive stud can substantially fill the opening. A majority of the conductive stud can lie within the opening. In still another embodiment, a process for forming an electronic device can include forming a conductive stud within the opening wherein from a top view, the conductive stud lies substantially completely within the opening. The process can also include forming a second barrier layer overlying the conductive stud.Type: ApplicationFiled: October 11, 2010Publication date: February 3, 2011Applicant: Freescale Semiconductor, Inc.Inventors: Lakshmi N. Ramanathan, Tien Yu T. Lee, Jinbang Tang
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Patent number: 7812448Abstract: An electronic device can include an interconnect level (16) including a bonding pad region (110). An insulating layer (18) can overlie the interconnect level (16) and include an opening (112, 24) over the bonding pad region (110). In one embodiment, a conductive stud (34) can lie within the opening (112, 24) and can be substantially encapsulated. In another embodiment, the electronic device can include a barrier layer (22) lying along a side and a bottom of the opening (112, 24) and a conductive stud (34) lying within the opening (112, 24). The conductive stud (34) can substantially fill the opening (112, 24). A majority of the conductive stud (34) can lie within the opening (112, 24). In still another embodiment, a process for forming an electronic device can include forming a conductive stud (34) within the opening (112, 24) wherein the conductive stud (34) lies substantially completely within the opening (112, 24).Type: GrantFiled: August 7, 2006Date of Patent: October 12, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Lakshmi N. Ramanathan, Tien Yu T. Lee, Jinbang Tang
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Publication number: 20090032933Abstract: Redistributed Chip Packaging with Thermal Contact to Device Backside An integrated circuit assembly includes a panel including an semiconductor device at least partially surrounded by an encapsulant. A panel upper surface and a device active surface are substantially coplanar. The assembly further includes one or more interconnect layers overlying the panel upper surface. Each of the interconnect layers includes an insulating film having contacts formed therein an interconnect metallization formed thereon. A lower surface of the panel is substantially coplanar with either a backside of the device or a lower surface of a thermally and electrically conductive slab that has an upper surface in thermal contact with the device backside. The assembly may also include a set of panel vias.Type: ApplicationFiled: July 31, 2007Publication date: February 5, 2009Inventors: Neil T. Tracht, Darrel R. Frear, James R. Griffiths, Lizabeth Ann A. Keser, Tien Yu T. Lee, Elie A. Maalouf
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Patent number: 7405102Abstract: A multi-layer structure (102) includes a first build-up layer structure (202) configured to connect to a heat-generating module (120), a second build-up layer structure (206) configured to connect to a substrate, and a middle layer (204) provided between the first build-up layer structure and the second build-up layer structure, the middle layer including at least one semiconductor component (110) and a heat spreader (130). A first set of thermal vias (210) extend through the first build-up layer structure to the heat spreader, and a second set of thermal vias (2100 extend through the second build-up layer structure to the heat spreader, wherein at least a portion of the first set of thermal vias is in thermal contact with the heat-generating module.Type: GrantFiled: June 9, 2006Date of Patent: July 29, 2008Assignee: Freescale Semiconductor, Inc.Inventors: Tien Yu T. Lee, Craig S. Amrine, Victor A. Chiriac, Lizabeth Ann Keser, George R. Leal, Robert J. Wenzel
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Publication number: 20080029887Abstract: An electronic device can include an interconnect level (16) including a bonding pad region (110). An insulating layer (18) can overlie the interconnect level (16) and include an opening (112, 24) over the bonding pad region (110). In one embodiment, a conductive stud (34) can lie within the opening (112, 24) and can be substantially encapsulated. In another embodiment, the electronic device can include a barrier layer (22) lying along a side and a bottom of the opening (112, 24) and a conductive stud (34) lying within the opening (112, 24). The conductive stud (34) can substantially fill the opening (112, 24). A majority of the conductive stud (34) can lie within the opening (112, 24). In still another embodiment, a process for forming an electronic device can include forming a conductive stud (34) within the opening (112, 24) wherein from a top view, the conductive stud (34) lies substantially completely within the opening (112, 24).Type: ApplicationFiled: August 7, 2006Publication date: February 7, 2008Applicant: Freescale Semiconductor, Inc.Inventors: Lakshmi N. Ramanathan, Tien Yu T. Lee, Jinbang Tang
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Publication number: 20070284704Abstract: A package assembly 200 includes a semiconductor die (e.g., an RF power amplifier) 208 fixed within the cavity of a conductive leadframe 204 using a thermally and electrically-conductive adhesive material 209. The semiconductor die 209 has a first side and a second side, wherein the first side includes at least one active area, and the second side includes at least one contact region. The conductive leadframe (e.g., a copper leadframe) 204 has two planar surfaces and a cavity formed therein. The adhesive material 209 is configured to couple the semiconductor die 208 within the cavity of the conductive leadframe 204 such that the first side of the semiconductor die is substantially coplanar with the first surface of the conductive leadframe.Type: ApplicationFiled: June 9, 2006Publication date: December 13, 2007Inventors: George R. Leal, Victor A. Chiriac, Tien Yu T. Lee, Marc A. Mangrum, Robert J. Wenzel
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Publication number: 20070284711Abstract: A multi-layer structure (102) includes a first build-up layer structure (202) configured to connect to a heat-generating module (120), a second build-up layer structure (206) configured to connect to a substrate, and a middle layer (204) provided between the first build-up layer structure and the second build-up layer structure, the middle layer including at least one semiconductor component (110) and a heat spreader (130). A first set of thermal vias (210) extend through the first build-up layer structure to the heat spreader, and a second set of thermal vias (2100 extend through the second build-up layer structure to the heat spreader, wherein at least a portion of the first set of thermal vias is in thermal contact with the heat-generating module.Type: ApplicationFiled: June 9, 2006Publication date: December 13, 2007Inventors: Tien Yu T. Lee, Craig S. Amrine, Victor A. Chiriac, Lizabeth Ann Keser, George R. Leal, Robert J. Wenzel
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Patent number: 6040624Abstract: A chip scale power semiconductor device (16) provides improved heat dissipation. A semiconductor die (19) is mounted in a first region of a substrate (18). The substrate is extended to a second region for disposing terminals (38) to make external connections to the semiconductor device. Conductors (34) formed on the substrate electrically couple the semiconductor die to the terminals. The substrate is extended for a predetermined distance to separate the second region from the first region for isolating the temperature of the semiconductor die from the local temperature at the terminals.Type: GrantFiled: October 2, 1997Date of Patent: March 21, 2000Assignee: Motorola, Inc.Inventors: Benjamin C. Chambers, William R. Blood, Jr., Tien-Yu T. Lee
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Patent number: 5915463Abstract: A heat dissipation apparatus (51) has a lid (12) and an optimized fin arrangement (16) located in a cavity (57) of a base (11). Semiconductor chips (41, 42, 43, 44, 45, and 46) are coupled to the lid (12), and a heat conducting medium (47) is forced into the cavity (57) through a port (13) and out of the cavity (57) through a different port (14). Heat generated by the semiconductor chips (41, 42, 43, 44, 45, and 46) is thermally conducted into the fin arrangement (16) and then transferred into the heat conducting medium (47).Type: GrantFiled: March 23, 1996Date of Patent: June 29, 1999Assignee: Motorola, Inc.Inventors: Guillermo L. Romero, Tien-Yu T. Lee
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Patent number: 5487355Abstract: A method of growing semiconductor crystals including inserting a single crystal seed (14) of a semiconductor material into a melt (12) and pulling the seed (14) at a first rate to gradually grow an elongated, single crystal first neck (15), altering the pulling rate to a second rate, slower than the first rate, to grow a shoulder (17) on the first neck (15) with a diameter greater than the first neck (15), continuing to pull at the second rate to form a second neck (18) with a diameter equal to the diameter of the shoulder (17), and altering the pulling rate to a third rate, slower than the second rate, to grow a single crystal elongated body (20) of the semiconductor material.Type: GrantFiled: March 3, 1995Date of Patent: January 30, 1996Assignee: Motorola, Inc.Inventors: Herng-Der Chiou, Tien-Yu T. Lee
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Patent number: 5391285Abstract: An apparatus plates metal bumps of uniform height on one surface of a semiconductor wafer (32). A plating tank (12) contains the plating solution. The plating solution is filtered (16) and pumped (14) through an inlet (22) to an anode plate (24) within plating cell (20). The anode plate has a solid center area to block direct in-line passage of the plating solution, and concentric rings of openings closer to its perimeter to pass the plating solution. The distance between the inlet and the anode plate is adjustable with supports to create a uniform flow of the plating solution to the surface of the semiconductor wafer for uniform plating of the array of metal bumps (30). The plating cell contains an adjustable sidewall extension (26) to set the proper distance between the anode plate and the semiconductor wafer.Type: GrantFiled: February 25, 1994Date of Patent: February 21, 1995Assignee: Motorola, Inc.Inventors: William H. Lytle, Tien-Yu T. Lee, Bennett L. Hileman
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Patent number: 5050114Abstract: A method for predicting the optimum operating conditions for a two-phase liquid cooling environment using simulation software utilizes a data base containing properties for several liquid coolants. A coolant is selected from the data base, and a cooling scheme is designated. Physical properties related to an integrated circuit are entered, includinhg circuit surface heat flux. A coolant temperature and flow rate are selected. The operating conditions for the integrated circuit are calculated based upon the cooling scheme and test conditions, including calculating boiling incipience heat flux and critical heat flux. The circuit surface heat flux is compared to the boiling incipience heat flux and critical heat flux to determine if the test conditions provide for nucleate boiling. The calculations are repeated for additional temperatures and flow rates. Results are displayed in printed or graphic form.Type: GrantFiled: September 17, 1990Date of Patent: September 17, 1991Assignee: Motorola, Inc.Inventor: Tien-Yu T. Lee