Patents by Inventor Tim Bales
Tim Bales has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9231011Abstract: Imaging systems may be provided with stacked-chip image sensors. A stacked-chip image sensor may include a vertical chip stack that includes an array of image pixels, analog control circuitry and storage and processing circuitry. The array of image pixels, the analog control circuitry, and the storage and processing circuitry may be formed on separate, stacked semiconductor substrates or may be formed in a vertical stack on a common semiconductor substrate. The image pixel array may be coupled to the control circuitry using vertical metal interconnects. The control circuitry may route pixel control signals and readout image data signals over the vertical metal interconnects. The control circuitry may provide digital image data to the storage and processing circuitry over additional vertical conductive interconnects coupled between the control circuitry and the storage and processing circuitry. The storage and processing circuitry may be configured to store and/or process the digital image data.Type: GrantFiled: November 17, 2014Date of Patent: January 5, 2016Assignee: Semiconductor Components Industries, LLCInventors: Johannes Solhusvik, Tim Bales
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Patent number: 9190444Abstract: Imaging systems may be provided with stacked-chip image sensors. A stacked-chip image sensor may include a vertical chip stack that includes an array of image pixels, analog control circuitry and storage and processing circuitry. The array of image pixels, the analog control circuitry, and the storage and processing circuitry may be formed on separate, stacked semiconductor substrates or may be formed in a vertical stack on a common semiconductor substrate. The image pixel array may be coupled to the control circuitry using vertical metal interconnects. The control circuitry may route pixel control signals and readout image data signals over the vertical metal interconnects. The control circuitry may provide digital image data to the storage and processing circuitry over additional vertical conductive interconnects coupled between the control circuitry and the storage and processing circuitry. The storage and processing circuitry may be configured to store and/or process the digital image data.Type: GrantFiled: November 17, 2014Date of Patent: November 17, 2015Assignee: Semiconductor Components Industries, LLCInventors: Johannes Solhusvik, Tim Bales
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Publication number: 20150115134Abstract: Imaging systems may be provided with stacked-chip image sensors. A stacked-chip image sensor may include a vertical chip stack that includes an array of image pixels, analog control circuitry and storage and processing circuitry. The array of image pixels, the analog control circuitry, and the storage and processing circuitry may be formed on separate, stacked semiconductor substrates or may be formed in a vertical stack on a common semiconductor substrate. The image pixel array may be coupled to the control circuitry using vertical metal interconnects. The control circuitry may route pixel control signals and readout image data signals over the vertical metal interconnects. The control circuitry may provide digital image data to the storage and processing circuitry over additional vertical conductive interconnects coupled between the control circuitry and the storage and processing circuitry. The storage and processing circuitry may be configured to store and/or process the digital image data.Type: ApplicationFiled: November 17, 2014Publication date: April 30, 2015Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Johannes Solhusvik, Tim Bales
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Patent number: 8890047Abstract: Imaging systems may be provided with stacked-chip image sensors. A stacked-chip image sensor may include a vertical chip stack that includes an array of image pixels, analog control circuitry and storage and processing circuitry. The array of image pixels, the analog control circuitry, and the storage and processing circuitry may be formed on separate, stacked semiconductor substrates or may be formed in a vertical stack on a common semiconductor substrate. The image pixel array may be coupled to the control circuitry using vertical metal interconnects. The control circuitry may route pixel control signals and readout image data signals over the vertical metal interconnects. The control circuitry may provide digital image data to the storage and processing circuitry over additional vertical conductive interconnects coupled between the control circuitry and the storage and processing circuitry. The storage and processing circuitry may be configured to store and/or process the digital image data.Type: GrantFiled: February 21, 2012Date of Patent: November 18, 2014Assignee: Aptina Imaging CorporationInventors: Johannes Solhusvik, Tim Bales
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Publication number: 20130068929Abstract: Imaging systems may be provided with stacked-chip image sensors. A stacked-chip image sensor may include a vertical chip stack that includes an array of image pixels, analog control circuitry and storage and processing circuitry. The array of image pixels, the analog control circuitry, and the storage and processing circuitry may be formed on separate, stacked semiconductor substrates or may be formed in a vertical stack on a common semiconductor substrate. The image pixel array may be coupled to the control circuitry using vertical metal interconnects. The control circuitry may route pixel control signals and readout image data signals over the vertical metal interconnects. The control circuitry may provide digital image data to the storage and processing circuitry over additional vertical conductive interconnects coupled between the control circuitry and the storage and processing circuitry. The storage and processing circuitry may be configured to store and/or process the digital image data.Type: ApplicationFiled: February 21, 2012Publication date: March 21, 2013Inventors: Johannes Solhusvik, Tim Bales
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Publication number: 20080106298Abstract: A system and method to correct or cancel MOS linear region impedance curvature employing an analog solution to trim out the MOS linear region impedance curvature while accommodating PVT spreads in values of internal or external precision resistors. The linear region curvature correction may be obtained by using two MOS transistors in the pad driver/buffer and operating the transistors so as to proportionately increase output impedance of one of them when the output impedance of the other decreases, and vice versa. A linear pad impedance may be maintained over a range of Vpad values, while also maintaining the Vgs supplied to pad driver transistors at its maximum possible value to obtain greater linearity.Type: ApplicationFiled: October 16, 2007Publication date: May 8, 2008Inventor: Tim Bales
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Publication number: 20080061820Abstract: A system and method to correct or cancel MOS linear region impedance curvature employing an analog solution to trim out the MOS linear region impedance curvature while accommodating PVT spreads in values of internal or external precision resistors. The linear region curvature correction may be obtained by using two MOS transistors in the pad driver/buffer and operating the transistors so as to proportionately increase output impedance of one of them when the output impedance of the other decreases, and vice versa. A linear pad impedance may be maintained over a range of Vpad values, while also maintaining the Vgs supplied to pad driver transistors at its maximum possible value to obtain greater linearity.Type: ApplicationFiled: August 31, 2007Publication date: March 13, 2008Inventor: Tim Bales
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Publication number: 20050178001Abstract: A semiconductor package assembly and method for electrically isolating modules, having a capacitor within the semiconductor package assembly. The package assembly and method are suitable for electrically isolating modules according to IEEE 1394.Type: ApplicationFiled: February 7, 2005Publication date: August 18, 2005Inventors: Sion Quinlan, Tim Bales
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Publication number: 20050145976Abstract: A semiconductor package assembly and method for electrically isolating modules, having a capacitor within the semiconductor package assembly. The package assembly and method are suitable for electrically isolating modules according to IEEE 1394.Type: ApplicationFiled: January 20, 2005Publication date: July 7, 2005Inventors: Sion Quinlan, Tim Bales
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Publication number: 20050130346Abstract: A semiconductor package assembly and method for electrically isolating modules, having a capacitor within the semiconductor package assembly. The package assembly and method are suitable for electrically isolating modules according to IEEE 1394.Type: ApplicationFiled: January 20, 2005Publication date: June 16, 2005Inventors: Sion Quinlan, Tim Bales
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Publication number: 20050130347Abstract: A semiconductor package assembly and method for electrically isolating modules, having a capacitor within the semiconductor package assembly. The package assembly and method are suitable for electrically isolating modules according to IEEE 1394.Type: ApplicationFiled: January 20, 2005Publication date: June 16, 2005Inventors: Sion Quinlan, Tim Bales
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Publication number: 20050130348Abstract: A semiconductor package assembly and method for electrically isolating modules, having a capacitor within the semiconductor package assembly. The package assembly and method are suitable for electrically isolating modules according to IEEE 1394.Type: ApplicationFiled: January 20, 2005Publication date: June 16, 2005Inventors: Sion Quinlan, Tim Bales
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Publication number: 20050121754Abstract: A semiconductor package assembly and method for electrically isolating modules, having a capacitor within the semiconductor package assembly. The package assembly and method are suitable for electrically isolating modules according to IEEE 1394.Type: ApplicationFiled: January 20, 2005Publication date: June 9, 2005Inventors: Sion Quinlan, Tim Bales
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Publication number: 20050088199Abstract: A system and method to correct or cancel MOS linear region impedance curvature employing an analog solution to trim out the MOS linear region impedance curvature while accommodating PVT spreads in values of internal or external precision resistors. The linear region curvature correction may be obtained by using two MOS transistors in the pad driver/buffer and operating the transistors so as to proportionately increase output impedance of one of them when the output impedance of the other decreases, and vice versa. A linear pad impedance may be maintained over a range of Vpad values, while also maintaining the Vgs supplied to pad driver transistors at its maximum possible value to obtain greater linearity.Type: ApplicationFiled: March 19, 2004Publication date: April 28, 2005Inventor: Tim Bales
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Patent number: 6639424Abstract: An apparatus and associated method are provided for combining a dynamic logic gate and level shifting circuitry in an improved circuit. The combined dynamic logic gate and level shifting circuit of the invention includes a pair of logic gates each having an output and configured such that only one output of the pair is applied at a time to a respective one of a pair of output switching circuits coupled to receive the outputs of the logic gates, wherein a pair of inputs which transition in a first voltage range control the logic gates to produce an output which transitions in a second voltage range in response to the switching of the output switching circuits.Type: GrantFiled: August 31, 2001Date of Patent: October 28, 2003Assignee: Micron Technology, Inc.Inventor: Tim Bales
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Publication number: 20030042932Abstract: An apparatus and associated method are provided for combining a dynamic logic gate and level shifting circuitry in an improved circuit. The combined dynamic logic gate and level shifting circuit of the invention includes a pair of logic gates each having an output and configured such that only one output of the pair is applied at a time to a respective one of a pair of output switching circuits coupled to receive the outputs of the logic gates, wherein a pair of inputs which transition in a first voltage range control the logic gates to produce an output which transitions in a second voltage range in response to the switching of the output switching circuits.Type: ApplicationFiled: August 31, 2001Publication date: March 6, 2003Inventor: Tim Bales
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Patent number: 6137273Abstract: The present invention concerns a circuit (30; 50) for supplying a first current (I3) to an external element (3), this current having to be supplied with high precision at a desired nominal value. The current supply circuit includes a first transistor (T3) through which the first current flows, an operational amplifier (A2) to a first input of which a reference voltage (Vref) is supplied, and to an output of which a control signal from the first transistor is supplied, and an external resistor (Re1; Re2). These the circuit is characterized in that it further includes a second transistor (T4) through which a second current (I4; I4/m) flows, said second current also flowing through the external resistor. Such an arrangement of the circuit according to the present invention allow the value of the first current to be trimmed with great precision to its nominal value.Type: GrantFiled: October 15, 1998Date of Patent: October 24, 2000Assignee: EM Microelectronic-Marin SAInventors: Tim Bales, Serge Bitz