Abstract: A disk retention system includes a spindle motor assembly with a spindle motor and an electromagnet retainer coupled and rotatable therewith, and a disk media assembly including a disk medium and a ferromagnetic material coupled therewith, whereby the disk is retained on the spindle motor by an adjustable attractive magnetic force between the ferromagnetic material of the disk assembly and the electromagnet retainer of the motor assembly. The motor assembly may further include a pair of stationary electrically-conductive liquid or liquid metal slip rings and a pair of rotatable electrical contacts each electrically coupled with a respective slip ring and with the electromagnet retainer, where the slip rings may utilize a Gallium-Indium-Tin alloy.

Abstract: A cellular telephone is configured to perform procedures to protect against malfunction or damage to an HDD or other mass storage device in the cell phone, in response to receiving an indication of an incoming call. The protection procedures can include delaying one or more cell phone operations, and/or sending instructions to an HDD or other mass storage device including instructions to complete an operation, suspend an operation, park a head and/or spin down an HDD. In a cell phone which provides for extended playback, e.g., of audio or video, the cellular telephone preferably is configured to avoid interruptions of playback, e.g., during suspension or HDD operation.

Abstract: An improved disk drive architecture includes a microcontroller interface circuit connected between a drive microcontroller and a buffer controller. The microcontroller interface circuit includes address mapping registers for mapping at least one predetermined portion of directly addressable memory of the microcontroller to address locations of the drive's cache buffer. The buffer controller circuit includes an access arbitration circuit for arbitrating requests for access to the cache buffer by the drive's data sequencer, the drive's host interface controller and the drive's microcontroller. A microcontroller wait state generator responds to the access arbitration circuit by generating and applying a wait state sequence to the microcontroller until a request it makes for access to the cache buffer can be executed.

Abstract: A high capacity micro-Winchester disk drive is capable of storing approximately 120 megabytes of user data on each storage disk. A digital bus interface connects to data, control and status lines from a host computer, and a cache memory defines a plurality of programmable memory segments for disk data, host data and microcontroller data. The cache memory controller enables read-ahead, write-ahead, and automatic multiple block read and write operations to occur between the disk drive and the host without intervention of the disk drive's embedded microcontroller.

Abstract: A mass storage subsystem is connectable to a host computer via a host adapter and includes a subsystem bus extending from the host adapter to at least one base unit and a removable disk drive cartridge for use with the base unit. A control signal path extends between the base unit and the removable disk drive cartridge when it is installed and connected within the base unit. The disk drive cartridge includes a housing, at least one storage disk rotatably mounted within the housing, at least one data transducer head within the housing and positionable by a head positioner at selected concentric data storage tracks defined on a storage surface of the storage disk. A bus interface circuit is provided for directly connecting to the subsystem bus when the cartridge is installed and connected within the base unit, and a cartridge controller is provided for controlling operations of the bus interface circuit and the head positioner and for communicating with the base unit via the control signal path.

Abstract: A method divides a recurrent digital clocking signal into a quotient digital signal having a substantially symmetrical duty cycle within a range of programmable quotients, the quotients being selectable in single increments of the recurrent digital clocking signal within a range as selected by a divisor.