Patents by Inventor Timo AILA

Timo AILA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9405508
    Abstract: This disclosure is directed to systems and methods for sorting data in which pre-sorting operations are performed on keys prior to those keys being reordered within memory. One example method includes generating, for each of a plurality of keys, an associated modified key. This operation is an example pre-sorting operation that occurs prior to any reordering of the keys. Once the modified keys are generated, the modified keys and/or associated information are processed in order to change the ordering of the keys in memory.
    Type: Grant
    Filed: May 21, 2013
    Date of Patent: August 2, 2016
    Assignee: NVIDIA CORPORATION
    Inventors: Tero Tapani Karras, Timo Aila
  • Patent number: 9305392
    Abstract: Techniques are disclosed for tracing a ray within a parallel processing unit. A first thread receives a ray or a ray segment for tracing and identifies a first node within an acceleration structure associated with the ray, where the first node is associated with a volume of space traversed by the ray. The thread identifies the child nodes of the first node, where each child node is associated with a different sub-volume of space, and each sub-volume is associated with a corresponding ray segment. The thread determines that two or more nodes are associated with sub-volumes of space that intersect the ray segment. The thread selects one of these nodes for processing by the first thread and another for processing by a second thread. One advantage of the disclosed technique is that the threads in a thread group perform ray tracing more efficiently in that idle time is reduced.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: April 5, 2016
    Assignee: NVIDIA Corporation
    Inventors: David Luebke, Timo Aila, Jacopo Pantaleoni, David Tarjan
  • Patent number: 9269182
    Abstract: A method for identifying entry points of a hierarchical structure having a plurality of nodes includes the operations selecting a node of a hierarchical structure and testing it for identification as an entry point. The node is identified as an entry point, and the selection, testing, and identification operations are repeated for at least one additional node of the hierarchical structure to identify at least a second node as a respective second entry point for the hierarchical structure.
    Type: Grant
    Filed: September 5, 2008
    Date of Patent: February 23, 2016
    Assignee: NVIDIA Corporation
    Inventors: Timo Aila, Samuli Laine
  • Patent number: 9158595
    Abstract: One embodiment sets forth a technique for scheduling the execution of ordered critical code sections by multiple threads. A multithreaded processor includes an instruction scheduling unit that is configured to schedule threads to process ordered critical code sections. A ordered critical code section is preceded by a barrier instruction and when all of the threads have reached the barrier instruction, the instruction scheduling unit controls the thread execution order by selecting each thread for execution based on logical identifiers associated with the threads. The logical identifiers are mapped to physical identifiers that are referenced by the multithreaded processor during execution of the threads. The logical identifiers are used by the instruction scheduling unit to control the order in which the threads execute the ordered critical code section.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: October 13, 2015
    Assignee: NVIDIA Corporation
    Inventors: John Erik Lindholm, Tero Tapani Karras, Samuli Matias Laine, Timo Aila
  • Patent number: 9153068
    Abstract: A method for reducing the number of samples tested for rendering a screen space region of an image includes constructing a trajectory of a primitive extending in an image which is to be rendered. A bounding volume is constructed for a screen space region of the image, the bounding volume characterized as having a bound in a non-screen space dimension which is defined as a function of the primitive's trajectory. The bounding volume is further characterized as overlapping a portion of the screen space region which is to be rendered. One or more sample points which are located within the screen space region, and which are not overlapped by the bounding volume are excluded from testing.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: October 6, 2015
    Assignee: NVIDIA CORPORATION
    Inventors: Samuli Laine, Tero Karras, Jaakko Lehtinen, Timo Aila
  • Patent number: 9147270
    Abstract: A method for reducing the number of samples tested for rendering a screen space region of an image includes constructing a trajectory of a primitive in a three dimensional coordinate system, the coordinate system including a screen space dimension, a lens dimension and a time dimension. A bounding volume is constructed for a screen space region which is to be rendered, the bounding volume overlapping a portion of the screen space region. The bounding volume is defined according to a plurality of bounding planes which extend in the three dimensional coordinate system, whereby the bounding planes are determined as a function of the trajectory of the primitive. One or more sample points which are located within the screen space region, and which are not overlapped by the bounding volume are excluded from testing.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: September 29, 2015
    Assignee: NVIDIA CORPORATION
    Inventors: Jaakko Lehtinen, Timo Aila, Samuli Laine
  • Patent number: 9142043
    Abstract: A method for reducing the number of samples tested for rendering a screen space region of an image includes constructing a trajectory of a primitive extending within an image which is to be rendered. A bounding volume is constructed for a screen space region of the image, the bounding volume characterized as having a bound in a non-screen space dimension which is defined as a function of the primitive's trajectory. The bounding volume is further characterized as overlapping a portion of the screen space region which is to be rendered. One or more sample points which are located within the screen space region, and which are not overlapped by the bounding volume are excluded from testing.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: September 22, 2015
    Assignee: NVIDIA CORPORATION
    Inventors: Timo Aila, Samuli Laine, Tero Karras, Jaakko Lehtinen, Peter Shirley
  • Patent number: 8977049
    Abstract: A method for estimating signal-dependent noise includes defining a plurality of pixel groups from among the image pixels. The method further includes computing, for one or more signal levels of the image, a difference value between two pixel groups, whereby a respective one or more difference values are computed collectively. The method determines an estimated noise response of the image as a function of the one or more computed difference values.
    Type: Grant
    Filed: January 8, 2010
    Date of Patent: March 10, 2015
    Assignee: NVIDIA Corporation
    Inventors: Timo Aila, Samuli Laine
  • Patent number: 8970584
    Abstract: A bounding box-based method for reducing the number of samples tested for rendering a screen space region of an image includes determining a trajectory of a primitive in screen space for an image which is to be rendered and constructing an axis-aligned bounding box for the screen space region. The axis-aligned bounding box includes a bound in a non-screen dimension that is defined as a function of the screen space trajectory of the primitive, and overlaps a portion of the screen space region. One or more sample points which are located within the screen space region, and which are not overlapped by the axis-aligned bounding box are excluded from testing.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: March 3, 2015
    Assignee: Nvidia Corporation
    Inventors: Timo Aila, Jaakko Lehtinen, Peter Shirley, Samuli Laine
  • Publication number: 20140351276
    Abstract: This disclosure is directed to systems and methods for sorting data in which pre-sorting operations are performed on keys prior to those keys being reordered within memory. One example method includes generating, for each of a plurality of keys, an associated modified key. This operation is an example pre-sorting operation that occurs prior to any reordering of the keys. Once the modified keys are generated, the modified keys and/or associated information are processed in order to change the ordering of the keys in memory.
    Type: Application
    Filed: May 21, 2013
    Publication date: November 27, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Tero Tapani Karras, Timo Aila
  • Patent number: 8842931
    Abstract: A system, method, and computer program product are provided for reducing noise in an image using depth-based on sweeping over image samples. In use, each noisy pixel of an image having noise is identified. Additionally, for each noisy pixel, at least one sample included in each of a plurality of neighboring pixels to the noisy pixel is identified. Furthermore, the samples are swept over at least partially in a depth-based order to identify a value for the noisy pixel that reduces the noise.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: September 23, 2014
    Assignee: NVIDIA Corporation
    Inventors: Peter Schuyler Shirley, Timo Aila, Jonathan Michael Cohen, Eric B. Enderton, Samuli Laine, Morgan McGuire, David Patrick Luebke
  • Publication number: 20140168228
    Abstract: Techniques are disclosed for tracing a ray within a parallel processing unit. A first thread receives a ray or a ray segment for tracing and identifies a first node within an acceleration structure associated with the ray, where the first node is associated with a volume of space traversed by the ray. The thread identifies the child nodes of the first node, where each child node is associated with a different sub-volume of space, and each sub-volume is associated with a corresponding ray segment. The thread determines that two or more nodes are associated with sub-volumes of space that intersect the ray segment. The thread selects one of these nodes for processing by the first thread and another for processing by a second thread. One advantage of the disclosed technique is that the threads in a thread group perform ray tracing more efficiently in that idle time is reduced.
    Type: Application
    Filed: December 13, 2012
    Publication date: June 19, 2014
    Applicant: NVIDIA Corporation
    Inventors: David LUEBKE, Timo AILA, Jacopo PANTALEONI, David TARJAN
  • Publication number: 20140168238
    Abstract: Techniques are disclosed for tracing a ray within a parallel processing unit. A first thread receives a ray or a ray segment for tracing and identifies a first node within an acceleration structure associated with the ray, where the first node is associated with a volume of space traversed by the ray. The thread identifies the child nodes of the first node, where each child node is associated with a different sub-volume of space, and each sub-volume is associated with a corresponding ray segment. The thread determines that two or more nodes are associated with sub-volumes of space that intersect the ray segment. The thread selects one of these nodes for processing by the first thread and another for processing by a second thread. One advantage of the disclosed technique is that the threads in a thread group perform ray tracing more efficiently in that idle time is reduced.
    Type: Application
    Filed: December 13, 2012
    Publication date: June 19, 2014
    Applicant: NVIDIA Corporation
    Inventors: David LUEBKE, Timo AILA, Jacopo PANTALEONI, David TARJAN
  • Publication number: 20140123150
    Abstract: One embodiment sets forth a technique for scheduling the execution of ordered critical code sections by multiple threads. A multithreaded processor includes an instruction scheduling unit that is configured to schedule threads to process ordered critical code sections. A ordered critical code section is preceded by a barrier instruction and when all of the threads have reached the barrier instruction, the instruction scheduling unit controls the thread execution order by selecting each thread for execution based on logical identifiers associated with the threads. The logical identifiers are mapped to physical identifiers that are referenced by the multithreaded processor during execution of the threads. The logical identifiers are used by the instruction scheduling unit to control the order in which the threads execute the ordered critical code section.
    Type: Application
    Filed: October 25, 2012
    Publication date: May 1, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: John Erik LINDHOLM, Tero Tapani KARRAS, Samuli Matias LAINE, Timo AILA
  • Publication number: 20140071129
    Abstract: A method of generating an image. The method includes simulating a presence of at least one light source within a virtualized three dimensional space. Within the virtualized three dimensional space, a light sensing plane is defined. The light sensing plane includes a matrix of a number of pixels to be displayed on a display screen. The method further includes using a light transport procedure, computing a gradient value for each pixel of the matrix to produce a number of gradient values. The gradient computation involves selecting a plurality of light path pairs that contribute to a pixel wherein the selection is biased towards selection of more light paths that pass through pixels having larger gradient values. The plurality of gradient values are converted to a plurality of light intensity values which represent the image.
    Type: Application
    Filed: December 28, 2012
    Publication date: March 13, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Jaakko Lehtinen, Timo Aila, Samuli Laine, Tero Karras, David Luebke
  • Patent number: 8564589
    Abstract: A method for performing a ray-box intersection test includes forming a span extending between a first plane-ray intersection point and a second plane-ray intersection point, and increasing the span by relocating to a new position at least one of the first and second plane-ray intersection points. A box intersection span is constructed using the increased span, and the box intersection span, which corresponds to a node in a hierarchical acceleration structure, is tested for intersection with the ray.
    Type: Grant
    Filed: May 17, 2010
    Date of Patent: October 22, 2013
    Assignee: NVIDIA Corporation
    Inventors: Timo Aila, Samuli Laine, John Erik Lindholm
  • Patent number: 8555036
    Abstract: A system includes a processor having an instruction register for storing an instruction having a predefined opcode, a predicate register for storing a predicate condition to select an output register for a result of the instruction, a first output register, and a second output register. The processor further includes processor circuitry operable to execute the instruction to produce a result, and processor circuitry operable to store the result of the instruction in the first output register if the predicate condition to select the output is true, and to store the second output register if the predicate condition to select the output is false. A single instruction is used to produce the result, and to store the result of the instruction.
    Type: Grant
    Filed: May 17, 2010
    Date of Patent: October 8, 2013
    Assignee: NVIDIA Corporation
    Inventors: Timo Aila, Samuli Laine
  • Patent number: 8502819
    Abstract: A method for performing a ray tracing node traversal operation in an image rendering process includes traversing a plurality of nodes within spatial hierarchy that represents a scene which is to be rendered, the spatial hierarchy including two or more hierarchy levels, each hierarchy level including one or more nodes. A number representing the number of nodes traversed in each one of a plurality of different hierarchy levels is stored, wherein each number is represented by at least one bit in a multi-bit binary sequence.
    Type: Grant
    Filed: May 17, 2010
    Date of Patent: August 6, 2013
    Assignee: NVIDIA Corporation
    Inventors: Timo Aila, Samuli Laine, John Erik Lindholm
  • Patent number: 8478071
    Abstract: A method for constructing a motion-compensated composite image of a scene includes acquiring a plurality of images of a scene over time, the plurality of images including an earlier-acquired image of the scene and a later-acquired image scene. The relative motion between the earlier and later acquired images are estimated, and an exposure parameter is computed based upon the estimated relative motion occurring between the earlier and later acquired images. A new image of the scene is acquired using the computed exposure parameter, and the earlier, later, and newly acquired images are combined to produce a motion-compensated composite image of the scene.
    Type: Grant
    Filed: December 16, 2009
    Date of Patent: July 2, 2013
    Assignee: NVIDIA Corporation
    Inventors: Timo Aila, Samuli Laine
  • Patent number: 8472455
    Abstract: A method for performing node traversal operations of a treelet-composed hierarchical structure includes allocating a queue for each of the plurality of treelets, each queue operable to store ray-states entering a respective one of the treelets. The method additionally includes determining that a ray-state exits a first treelet of the hierarchical structure and enters a second treelet of the hierarchical structure. The method further includes forwarding the ray-state entering the second treelet to a processing element for processing therein, wherein the queue allocated to store ray-states entering the second treelet is bypassed.
    Type: Grant
    Filed: January 8, 2010
    Date of Patent: June 25, 2013
    Assignee: NVIDIA Corporation
    Inventors: Timo Aila, Tero Karras