Patents by Inventor Timo Stripf
Timo Stripf has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11934835Abstract: Validation of correct derivation of a parallel program from a sequential program for deployment of the parallel program to a plurality of processing units is described. The system receives the program code of the sequential program and the program code of the parallel program. A static analysis component computes a first control flow graph, and determines dependencies within the sequential program code. It further computes a further control flow graph for each thread or process of the parallel program and determines dependencies within the further control flow graphs. A checking component checks if the sequential program and the derived parallel program are semantically equivalent by comparing the respective first and further control flow graphs and respective dependencies. A release component declares a correct derivation state for the parallel program to qualify the parallel program for deployment if the derived parallel program and the sequential program are semantically equivalent.Type: GrantFiled: January 18, 2023Date of Patent: March 19, 2024Assignee: emmtrix Technologies GmbHInventor: Timo Stripf
-
Publication number: 20230153112Abstract: Validation of correct derivation of a parallel program from a sequential program for deployment of the parallel program to a plurality of processing units is described. The system receives the program code of the sequential program and the program code of the parallel program. A static analysis component computes a first control flow graph, and determines dependencies within the sequential program code. It further computes a further control flow graph for each thread or process of the parallel program and determines dependencies within the further control flow graphs. A checking component checks if the sequential program and the derived parallel program are semantically equivalent by comparing the respective first and further control flow graphs and respective dependencies. A release component declares a correct derivation state for the parallel program to qualify the parallel program for deployment if the derived parallel program and the sequential program are semantically equivalent.Type: ApplicationFiled: January 18, 2023Publication date: May 18, 2023Inventor: Timo Stripf
-
Patent number: 10592219Abstract: A compiler system, method and computer program product for optimizing a program is disclosed. The compiler includes an extractor module configured to extract, from an initial program code, a hierarchical task representation wherein each node of the hierarchical task representation corresponds to a potential unit of execution. The root node of the hierarchical task representation represents the entire initial program code and each child node represents a sub-set of units of execution of its respective parent node. It further has a parallelizer module configured to apply to the hierarchical task representation pre-defined parallelization rules associated with the processing device to automatically adjust the hierarchical task representation by assigning particular units of execution to particular processing units of the processing device and by inserting communication and/or synchronization in that the adjusted hierarchical task representation reflects parallel program code for the processing device.Type: GrantFiled: August 22, 2018Date of Patent: March 17, 2020Assignee: Karlsruhe Institute of TechnologyInventors: Oliver Oey, Timo Stripf, Michael Rückauer, Jürgen Becker
-
Patent number: 10564947Abstract: A compiler system, computer-implemented method and computer program product for optimizing a program for multi-processor system execution. The compiler includes an interface component configured to load from a storage component program code to be executed by one or more processors (P1 to Pn) of a multi-processor system. The compiler further includes a static analysis component configured to determine data dependencies) within the program code, and further determines all basic blocks of the control flow graph providing potential insertion positions along paths where communication statements can be inserted to enable data flow between different processors at runtime. An evaluation function component of the compiler is configured to evaluate each potential insertion position with regards to its impact on program execution on the multi-processor system at runtime by using a predefined execution evaluation function.Type: GrantFiled: January 19, 2018Date of Patent: February 18, 2020Assignee: Karlsruhe Institute of TechnologyInventors: Johannes Meyer, Oliver Oey, Timo Stripf, Jürgen Becker
-
Publication number: 20190012155Abstract: A compiler system, method and computer program product for optimizing a program is disclosed. The compiler includes an extractor module configured to extract, from an initial program code, a hierarchical task representation wherein each node of the hierarchical task representation corresponds to a potential unit of execution. The root node of the hierarchical task representation represents the entire initial program code and each child node represents a sub-set of units of execution of its respective parent node. It further has a parallelizer module configured to apply to the hierarchical task representation pre-defined parallelization rules associated with the processing device to automatically adjust the hierarchical task representation by assigning particular units of execution to particular processing units of the processing device and by inserting communication and/or synchronization in that the adjusted hierarchical task representation reflects parallel program code for the processing device.Type: ApplicationFiled: August 22, 2018Publication date: January 10, 2019Inventors: Oliver Oey, Timo Stripf, Michael Rückauer, Jürgen Becker
-
Publication number: 20180143813Abstract: A compiler system, computer-implemented method and computer program product for optimizing a program for multi-processor system execution. The compiler includes an interface component configured to load from a storage component program code to be executed by one or more processors (P1 to Pn) of a multi-processor system. The compiler further includes a static analysis component configured to determine data dependencies) within the program code, and further determines all basic blocks of the control flow graph providing potential insertion positions along paths where communication statements can be inserted to enable data flow between different processors at runtime. An evaluation function component of the compiler is configured to evaluate each potential insertion position with regards to its impact on program execution on the multi-processor system at runtime by using a predefined execution evaluation function.Type: ApplicationFiled: January 19, 2018Publication date: May 24, 2018Inventors: Johannes Meyer, Oliver Oey, Timo Stripf, Jürgen Becker
-
Patent number: 9213677Abstract: A reconfigurable data processor architecture. The processor architecture includes: a first plurality of data processing elements, each having a respective synchronization unit, a data link structure adapted for dynamically interconnecting a number of the data processing elements, at least one configuration register, and at least one control unit in operative connection with the configuration register for controlling a contents thereof, wherein, based on the contents, the first plurality of data processing elements is adapted for temporarily constituting at runtime at least one group of one or more of said data processing elements from said first plurality of data processing elements dynamically via the data link structure. The synchronization units are adapted for synchronizing data processing by individual data processing elements within the group. The first plurality of data processing elements may be reconfigurably grouped and thus adapted to various data processing tasks at runtime.Type: GrantFiled: February 28, 2011Date of Patent: December 15, 2015Assignee: Karlsruher Institut für TechnologieInventors: Ralf Konig, Timo Stripf, Jurgen Becker
-
Publication number: 20120331268Abstract: A reconfigurable data processor architecture. The processor architecture includes: a first plurality of data processing elements, each having a respective synchronization unit, a data link structure adapted for dynamically interconnecting a number of the data processing elements, at least one configuration register, and at least one control unit in operative connection with the configuration register for controlling a contents thereof, wherein, based on the contents, the first plurality of data processing elements is adapted for temporarily constituting at runtime at least one group of one or more of said data processing elements from said first plurality of data processing elements dynamically via the data link structure. The synchronization units are adapted for synchronizing data processing by individual data processing elements within the group. The first plurality of data processing elements may be reconfigurably grouped and thus adapted to various data processing tasks at runtime.Type: ApplicationFiled: February 28, 2011Publication date: December 27, 2012Applicant: KARLSRUHER INSTITUT FUR TECHNOLOGIEInventors: Ralf Konig, Timo Stripf, Jurgen Becker