Abstract: A ceramic package substrate has a recess. This allows a device in that recess to be close to a die attached to the substrate's top side, for better performance. The device may be an array capacitor, an in-silicon voltage regulator, or another device or devices.

Abstract: In some embodiments, an individual sub-assembly containing a ceramic interposer, silicon voltage regulator, and array capacitor is presented. In this regard, an apparatus is introduced having a table-shaped ceramic interposer containing conductive traces, a silicon voltage regulator coupled with contacts on a first surface of the ceramic interposer, and an array capacitor coupled with contacts on a second surface of the ceramic interposer. Other embodiments are also disclosed and claimed.

Abstract: In some embodiments, a ceramic interposer with silicon voltage regulator and array capacitor combination for integrated circuit packages is presented. In this regard, an apparatus is introduced having a bowl-shaped ceramic interposer containing conductive traces, one or more silicon voltage regulator(s) coupled with contacts on a first surface of the ceramic interposer, and one or more array capacitor(s) coupled with contacts on a second surface of the ceramic interposer. Other embodiments are also disclosed and claimed.

Abstract: In some embodiments, an individual sub-assembly containing a ceramic interposer, silicon voltage regulator, and array capacitor is presented. In this regard, an apparatus is introduced having a table-shaped ceramic interposer containing conductive traces, a silicon voltage regulator coupled with contacts on a first surface of the ceramic interposer, and an array capacitor coupled with contacts on a second surface of the ceramic interposer. Other embodiments are also disclosed and claimed.

Abstract: A ceramic package substrate has a recess. This allows a device in that recess to be close to a die attached to the substrate's top side, for better performance. The device may be an array capacitor, an in-silicon voltage regulator, or another device or devices.

Abstract: A system having multiple on-chip logic analyzers (OCLA), each on-chip logic analyzer includes one or more word recognizers. The word recognizer includes a great deal of flexibility for the user, while being capable of implementation with very few gates. The word recognizer includes a Boolean logic portion in which a plurality of conditions can be dynamically segregated into a mutually exclusive set of groups. The conditions in each group are combined by means of a single Boolean function that is programmable. The resultant term (or product) from each group is combined with those of the other groups by a fixed selection of Boolean functions. The output of the Boolean logic section is provided to a counter/timer.

Abstract: A system is disclosed in which an on-chip logic analyzer (OCLA) is included in an integrated circuit, such as a microprocessor. During debug modes, one or more sets of an on-chip cache memory are disabled from use by other circuitry in the integrated circuit, and reserved exclusively for use by the OCLA. Data stored in the reserved cache set can then be read out by the OCLA, and placed in a register that can be accessed by other logic internal or external to the integrated circuit. If the integrated circuit is operating under normal mode, the cache memory set can be used in conventional fashion by other circuitry with in the integrated circuit to enhance performance.

Abstract: A system is disclosed in which an on-chip logic analyzer (OCLA) includes timestamp logic capable of providing clock cycle resolution of data entries using a relatively small number of bits. The timestamp logic includes a counter that is reset each time a store operation occurs. The counter counts the number of clock cycles since the previous store operation, and if enabled by the user, provides a binary signal to the memory that indicates the number of clock cycles since the previous store operation, which the memory stores with the state data. If the counter overflows before a store operation is requested, the timestamp logic may force a store operation so that the time between stores can be determined.

Abstract: An output port for an integrated circuit includes a bandwidth manager for assisting in the off-loading of internal state data during debug periods. The bandwidth manager operates to take internal state data at its normal frequency, and outputs at least the most important portions of that data to external logic. During periods when the output port is able to keep up with the internal sources being sampled, the bandwidth manager will cause all of the state data to be transmitted. If the output port becomes saturated, the bandwidth manager will select the most important portions of the internal state data to be transmitted off-chip, and will drop the less important information. The bandwidth manager is configured to operate dynamically based on the ability of the output port to keep up with the data being generated by the internal sources.

Abstract: A system is disclosed in which an on-chip logic analyzer (OCLA) includes a loop detector logic which receives incoming program counter (PC) data and detects when software loops exist. When a software loop is detected, the loop detector may be configured to store the first loop in memory, while all subsequent iterations are not stored, thus saving space in memory which would otherwise be consumed. The loop detector comprises a content addressable memory (CAM) which is enabled by a user programmed signal. The CAM may be configured with a programmable mask to determine which bits of the incoming PC data to compare with the CAM entries. The depth of the CAM also is programmable, to permit the CAM to be adjusted to cover the number of instructions in a loop.

Abstract: A system is disclosed in which an on-chip logic analyzer (OCLA) is included in an integrated circuit, such as a microprocessor. During debug modes, one or more sets of an on-chip cache memory are disabled from use by other circuitry in the integrated circuit, and reserved exclusively for use by the OCLA. Data stored in the reserved cache set can then be read out by the OCLA, and placed in a register that can be accessed by other logic internal or external to the integrated circuit. If the integrated circuit is operating under normal mode, the cache memory set can be used in conventional fashion by other circuitry with in the integrated circuit to enhance performance.

Abstract: An output port for an integrated circuit includes a bandwidth manager for assisting in the off-loading of internal state data during debug periods. The bandwidth manager operates to take internal state data at its normal frequency, and outputs at least the most important portions of that data to external logic. During periods when the output port is able to keep up with the internal sources being sampled, the bandwidth manager will cause all of the state data to be transmitted. If the output port becomes saturated, the bandwidth manager will select the most important portions of the internal state data to be transmitted off-chip, and will drop the less important information. The bandwidth manager is configured to operate dynamically based on the ability of the output port to keep up with the data being generated by the internal sources.

Abstract: A system is disclosed in which an on-chip logic analyzer (OCLA) includes timestamp logic capable of providing clock cycle resolution of data entries using a relatively small number of bits. The timestamp logic includes a counter that is reset each time a store operation occurs. The counter counts the number of clock cycles since the previous store operation, and if enabled by the user, provides a binary signal to the memory that indicates the number of clock cycles since the previous store operation, which the memory stores with the state data. If the counter overflows before a store operation is requested, the timestamp logic may force a store operation so that the time between stores can be determined.

Abstract: A system is disclosed in which an on-chip logic analyzer (OCLA) includes one or more word recognizers. The word recognizer includes a great deal of flexibility for the user, while being capable of implementation with very few gates. The word recognizer includes a Boolean logic portion in which a plurality of conditions can be dynamically segregated into a mutually-exclusive set of groups. The conditions in each group are combined by means of a single Boolean function that is programmable. The resultant term (or product) from each group is combined with those of the other groups by a fixed selection of Boolean functions. The output of the Boolean logic section is provided to a counter/timer. The counter/timer may be configured to either count the number of cycles that the match condition existed, or the number of times a match condition occurred. The counter can also be programmed to count total cycles when the match condition existed, or only consecutive cycles.

Abstract: A system is disclosed in which an on-chip logic analyzer (OCLA) includes a loop detector logic which receives incoming program counter (PC) data and detects when software loops exist. When a software loop is detected, the loop detector may be configured to store the first loop in memory, while all subsequent iterations are not stored, thus saving space in memory which would otherwise be consumed. The loop detector comprises a content addressable memory (CAM) which is enabled by a user programmed signal. The CAM may be configured with a programmable mask to determine which bits of the incoming PC data to compare with the CAM entries. The depth of the CAM also is programmable, to permit the CAM to be adjusted to cover the number of instructions in a loop.

Abstract: Method and apparatus for operating a multiprocessor data processing system (10) of the symmetric multiprocessor (SMP) type so as to continue the execution of a process running on a failed CPU (CPU-F). In response to a failure of one of the CPUs a first method performs the steps of: detecting that one of the CPUs has failed during the execution of a first process; extracting an internal processing state from the CPU-F; inserting the extracted processing state into a second, recovery CPU (CPU-R); and completing the execution of the first process with the CPU-R. During the time that the CPU-R executes the first process the CPU-R assumes the identity of the CPU-F, and furthermore assumes the ownership of any spinlocks that may have been owned by CPU-F. If selected from an active set of CPUs the operation of the CPU-R may be timeshared between the first process and a process that is running in the CPU-R.

Abstract: A Braille display system which encodes text and displays that text on a mechanical Braille display using a three-dimensional Braille code. Each symbol of the code has four frames each of which comprises a 4X2 dot-position array. When the text first appears on the Braille display, the system initially presents the top frame of each symbol. The system also includes a frame selection control by which a user can cause each of the remaining three frames of the relevant Braille symbol to appear individually on the Braille display. When each succeeding frame appears, it replaces the preceding frame of the same symbol. Thus, by using the frame selection control, a user can examine all four frames of each symbol at his discretion.

Abstract: A Braille display cell which may be embedded in one of a plurality of keys that are used to provide input to a digital data processor. Cursor controls identify a location in text containing characters, and, in response thereto, the processor produces a Braille actuation signal which identifies the character located at said position. The Braille actuation signal, in turn, generates a Braille indicator of the character on the Braille display cell. With the assistance of the cursor controls, the text can be scanned to cause the Braille indicators corresponding to the characters in the text to appear sequentially on the Braille display cell thereby displaying the text in Braille so that said text can be read tactilely.