Abstract: In certain arrangements and methods, a reset-able counter (100) produces multiple delay times as required by, for example, a finite state machine. The counter (100) counts a stored value by a configurable amount. That configurable amount is determined based upon the period of a clock cycle divided by a desired time unit. The value held by the counter does not represent a count of clock cycles, but rather a count of time units. In other aspects, a device generates fixed delays derived from a variable frequency input clock. The device includes a count circuit (100) and a comparator (114, 116). The number of time-units between consecutive clock edges of the input clock is stored, and the count circuit changes a current-count value by a corresponding amount, with the change being responsive to a clock edge of the input clock. The comparator (114, 116) compares the current-count value to a fixed value that represents a fixed delay time.

Abstract: In certain arrangements and methods, a reset-able counter (100) produces multiple delay times as required by, for example, a finite state machine. The counter (100) counts a stored value by a configurable amount. That configurable amount is determined based upon the period of a clock cycle divided by a desired time unit. The value held by the counter does not represent a count of clock cycles, but rather a count of time units. In other aspects, a device generates fixed delays derived from a variable frequency input clock. The device includes a count circuit (100) and a comparator (114, 116). The number of time-units between consecutive clock edges of the input clock is stored, and the count circuit changes a current-count value by a corresponding amount, with the change being responsive to a clock edge of the input clock. The comparator (114, 116) compares the current-count value to a fixed value that represents a fixed delay time.

Abstract: Various aspects of the present invention are directed to design modeling and/or processing of streaming data. According to an example embodiment, a system to model a hardware specification includes a platform (106) arranged to receive an input data stream and transmit an output data stream. The system also includes a source (102) for a streaming application adapted to provide the input data stream at a source data rate, a destination (104) for the streaming application adapted to consume the output data stream at a destination data rate, and a data channel (110) coupling the platform and a computer (108). The computer uses the hardware specification to generate intermediate data streams, which, in turn, are used to streamline the modeling for the platform.