Abstract: In some embodiments, a light emitting structure comprises a layered semiconductor stack comprising a first set of doped layers, a second layer, a light emitting layer positioned between the first set of doped layers and the second layer, and an electrical contact to the first set of doped layers. The first set of doped layers can comprise a first sub-layer, a second sub-layer, and a third sub-layer, wherein the third sub-layer is adjacent to the light emitting layer. The electrical contact can be coupled to the second sub-layer. The first, second and third sub-layers can be doped n-type, and an electrical conductivity of the second sub-layer can be higher than an electrical conductivity of the first and third sub-layers. The first, second and third sub-layers, the light emitting layer, and the second layer can each comprise a superlattice.

Abstract: A lightguide formed from a single substrate includes a substrate and a plurality of reflective structures disposed on the substrate. These reflective structures form one or more incouplers, exit pupil expanders, and outcouplers of the lightguide and are each configured to reflect light representative of an image. The lightguide also includes an effectively transparent overmold material disposed over the reflective structures that, together with at least a portion of the substrate, forms a first surface of the substrate. Further, the lightguide includes a second surface formed by removing at least a portion of the substrate via a material removal operation.

Abstract: A head unit device for controlling motion of an object includes a chamber filled with a shear thickening fluid (STF) and a piston. The piston is housed within the chamber and exerts pressure against the STF from a force applied to the piston from the object. The STF is configured to have a decreasing viscosity in response to a first range of shear rates and an increasing viscosity in response to a second range of shear rates. The piston includes at least one piston bypass between opposite sides of the piston that controls flow of the STF between the opposite sides of the piston to selectively react with a shear threshold effect of the first range of shear rates or the second range of shear rates.

Abstract: A neuromodulation therapy is delivered via at least one electrode implanted subcutaneously and superficially to a fascia layer superficial to a nerve of a patient. In one example, an implantable medical device is deployed along a superficial surface of a deep fascia tissue layer superficial to a nerve of a patient. Electrical stimulation energy is delivered to the nerve through the deep fascia tissue layer via implantable medical device electrodes.

Abstract: A neuromodulation therapy is delivered via at least one electrode implanted subcutaneously and superficially to a fascia layer superficial to a nerve of a patient. In one example, an implantable medical device is deployed along a superficial surface of a deep fascia tissue layer superficial to a nerve of a patient. Electrical stimulation energy is delivered to the nerve through the deep fascia tissue layer via implantable medical device electrodes.

Abstract: A waveguide including first and second sections has a first molded optic material forming a portion of the geometry of one or more Bragg gratings disposed on one surface of the first section of the waveguide. Similarly, a second molded optic material forming another portion of the geometry of one or more Bragg gratings is disposed on one surface of the second section of the waveguide. Further, a photopolymer material is deposited on the first molded optic material. As the first and second sections are coupled, a waveguide is formed with a layer of photopolymer material disposed in the waveguide with the layer of photopolymer material having a geometry defined by the first and second molded optic materials. Bragg grating holograms are then recorded in the layer of photopolymer material, resulting in a waveguide with a plurality of Bragg gratings.

Abstract: Disclosed is a gradient proportioning valve for liquid chromatography that includes a plurality of inlet ports configured to receive a plurality of fluids, a manifold connected to each of the plurality of inlet ports configured to mix the plurality of fluids in a controlled manner to provide a fluid composition, the manifold including a plurality of conduits internal to the manifold, each of the plurality of conduits receiving fluid through a respective one of the plurality of inlet ports, an actuation mechanism having a piston located within a bored structure surrounding the piston, the actuation mechanism configured to open and close at least one of the plurality of conduits in a controlled manner where the piston and the bored structure have a tight tolerance configured to create a fluid tight seal, and a common outlet port configured to receive the fluid composition.

Abstract: In an example implementation, a method includes receiving, at a computing device, borrower information and requested financing plan information. Likewise, a method includes outputting at least a portion of the received information to a second computing device and, after receiving an indication of a decision denying the requested financing plan, outputting at least a portion of the received information to a computing device associated with a lender and confirming, to a computing device associated with a borrower or a merchant that the information has been sent to the lender.

Abstract: In examples, a device comprises control logic configured to detect an idle cycle, an operand generator configured to provide a synthetic operand responsive to the detection of the idle cycle, and a computational circuit. The computational circuit is configured to, during the idle cycle, perform a first computation on the synthetic operand. The computational circuit is configured to, during an active cycle, perform a second computation on an architectural operand.

Abstract: The Multicore Bus Architecture (MBA) protocol includes a novel technique of sharing the same physical channel for all transaction types. Two channels, the Transaction Attribute Channel (TAC) and the Transaction Data Channel (TDC) are used. The attribute channel transmits bus transaction attribute information optionally including a transaction type signal, a transaction ID, a valid signal, a bus agent ID signal, an address signal, a transaction size signal, a credit spend signal and a credit return signal. The data channel connected a data subset of the signal lines of the bus separate from the attribute subset of signal lines the bus. The data channel optionally transmits a data valid signal, a transaction ID signal, a bus agent ID signal and a last data signal to mark the last data of a current bus transaction.

Abstract: A shielded in-line connector includes conductive first and second body portions, each with a securement feature, as well as conductive first and second clips. The first and second body portions are secured to one another to define an unshielded connector-receiving cavity as well as first and second shielded cable openings; each of the first and second shielded cable openings being proximate the respective clip securement feature. Each of the clip securement features includes a channel supportive of a respective shielded cable extending from each of the first and second shielded cable openings; each of the shielded cables having an exposed shield. The first and second clips are adjustably secured to a respective one of the first and second securement features to position the respective clip in direct contact with the exposed shield of the respective shielded cable.

Abstract: The Multicore Bus Architecture (MBA) protocol includes a novel technique of sharing the same physical channel for all transaction types. Two channels, the Transaction Attribute Channel (TAC) and the Transaction Data Channel (TDC) are used. The attribute channel transmits bus transaction attribute information optionally including a transaction type signal, a transaction ID, a valid signal, a bus agent ID signal, an address signal, a transaction size signal, a credit spend signal and a credit return signal. The data channel connected a data subset of the signal lines of the bus separate from the attribute subset of signal lines the bus. The data channel optionally transmits a data valid signal, a transaction ID signal, a bus agent ID signal and a last data signal to mark the last data of a current bus transaction.

Abstract: A technique for method for executing instructions in a processor includes receiving a first instruction, receiving a second instruction, identifying a functional unit specified by an opcode contained in an opcode field of the first instruction, selecting a field of the second instruction that contains predicate information based on the identified functional unit, and executing the first instruction in a conditional manner using the identified functional unit and the predicate information contained in the selected field of the second instruction.

Abstract: A technique for method for executing instructions in a processor includes receiving a first instruction, receiving a second instruction, identifying a functional unit specified by an opcode contained in an opcode field of the first instruction, selecting a field of the second instruction that contains predicate information based on the identified functional unit, and executing the first instruction in a conditional manner using the identified functional unit and the predicate information contained in the selected field of the second instruction.

Abstract: The Multicore Bus Architecture (MBA) protocol includes a novel technique of sharing the same physical channel for all transaction types. Two channels, the Transaction Attribute Channel (TAC) and the Transaction Data Channel (TDC) are used. The attribute channel transmits bus transaction attribute information optionally including a transaction type signal, a transaction ID, a valid signal, a bus agent ID signal, an address signal, a transaction size signal, a credit spend signal and a credit return signal. The data channel connected a data subset of the signal lines of the bus separate from the attribute subset of signal lines the bus. The data channel optionally transmits a data valid signal, a transaction ID signal, a bus agent ID signal and a last data signal to mark the last data of a current bus transaction.

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream recalled memory. Streams are started by one of two types of stream start instructions. A stream start ordinary instruction specifies a register storing a stream start address and a register of storing a stream definition template which specifies stream parameters. A stream start short-cut instruction specifies a register storing a stream start address and an implied stream definition template. A functional unit is responsive to a stream operand instruction to receive at least one operand from a stream head register. The stream template supports plural nested loops with short-cut start instructions limited to a single loop. The stream template supports data element promotion to larger data element size with sign extension or zero extension. A set of allowed stream short-cut start instructions includes various data sizes and promotion factors.

Abstract: A streaming engine employed in a digital data processor specifies fixed first and second read only data streams. Corresponding stream address generator produces address of data elements of the two streams. Corresponding steam head registers stores data elements next to be supplied to functional units for use as operands. The two streams share two memory ports. A toggling preference of stream to port ensures fair allocation. The arbiters permit one stream to borrow the other's interface when the other interface is idle. Thus one stream may issue two memory requests, one from each memory port, if the other stream is idle. This spreads the bandwidth demand for each stream across both interfaces, ensuring neither interface becomes a bottleneck.

Abstract: A flexible hybrid firewall architecture is disclosed. A system implementing such an architecture includes an access control register, a memory having at least a region to which access is controllable by the access control register, the access control register including first field that contains a privilege identifier (ID) and a plurality of additional fields, each additional field containing control bits corresponding to a respective one of a plurality of permission levels, and control circuitry that, in response to receiving a transaction containing a transaction privilege ID, a security indicator, and a privilege indicator, controls access to the region when the transaction privilege ID matches the privilege ID contained in the first field by using the control bits of a field of the additional fields that corresponds to a security level indicated by the security indicator and a privilege level indicated by the privilege indicator of the transaction.

Abstract: Disclosed embodiments relate to a streaming engine employed in, for example, a digital signal processor. A fixed data stream sequence including plural nested loops is specified by a control register. The streaming engine includes an address generator producing addresses of data elements and a steam head register storing data elements next to be supplied as operands. The streaming engine fetches stream data ahead of use by the central processing unit core in a stream buffer. Parity bits are formed upon storage of data in the stream buffer which are stored with the corresponding data. Upon transfer to the stream head register a second parity is calculated and compared with the stored parity. The streaming engine signals a parity fault if the parities do not match. The streaming engine preferably restarts fetching the data stream at the data element generating a parity fault.

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream recalled memory. Streams are started by one of two types of stream start instructions. A stream start ordinary instruction specifies a register storing a stream start address and a register of storing a stream definition template which specifies stream parameters. A stream start short-cut instruction specifies a register storing a stream start address and an implied stream definition template. A functional unit is responsive to a stream operand instruction to receive at least one operand from a stream head register. The stream template supports plural nested loops with short-cut start instructions limited to a single loop. The stream template supports data element promotion to larger data element size with sign extension or zero extension. A set of allowed stream short-cut start instructions includes various data sizes and promotion factors.