Patents by Inventor Timothy B. Prins

Timothy B. Prins has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Block mapping in high efficiency video coding compliant encoders and decoders
    Patent number: 10719433
    Abstract: An apparatus includes a central processing unit and a parallel processing unit. The parallel processing unit includes an array of software-configurable general purpose processors, a globally-shared memory, and a shared memory. Each of the software-configurable general purpose processors in the array of software-configurable general purpose processors has access to the globally-shared memory to execute one or more portions of at least one of (i) a decoding program, (ii) an encoding program, and (iii) an encoding and decoding program. The shared memory is accessible by the central processing unit to program the shared memory with a map array describing a position of block data in one or more associated arrays.
    Type: Grant
    Filed: November 12, 2018
    Date of Patent: July 21, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Jeffrey K. Lassahn, Timothy B. Prins
  • Sweep dependency based graphics processing unit block scheduling
    Patent number: 10306249
    Abstract: An apparatus includes a central processing unit and a parallel processing unit. The parallel processing unit generally includes an array of software-configurable general purpose processors, a globally shared memory, and a shared memory. Each of the software-configurable general purpose processors in the array of software-configurable general purpose processors generally has access to the globally shared memory to execute one or more portions of a decoding program. The shared memory is accessible by the central processing unit to program the shared memory with a schedule describing which of the one or more portions of the decoding program are to be executed by each of the software-configurable general purpose processors.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: May 28, 2019
    Assignee: AMAZON TECHNOLOGIES, INC.
    Inventors: Timothy B. Prins, Jeffrey K. Lassahn
  • BLOCK MAPPING IN HIGH EFFICIENCY VIDEO CODING COMPLIANT ENCODERS AND DECODERS
    Publication number: 20190087929
    Abstract: An apparatus includes a central processing unit and a parallel processing unit. The parallel processing unit includes an array of software-configurable general purpose processors, a globally-shared memory, and a shared memory. Each of the software-configurable general purpose processors in the array of software-configurable general purpose processors has access to the globally-shared memory to execute one or more portions of at least one of (i) a decoding program, (ii) an encoding program, and (iii) an encoding and decoding program. The shared memory is accessible by the central processing unit to program the shared memory with a map array describing a position of block data in one or more associated arrays.
    Type: Application
    Filed: November 12, 2018
    Publication date: March 21, 2019
    Inventors: Jeffrey K. Lassahn, Timothy B. Prins
  • Block mapping in high efficiency video coding compliant encoders and decoders
    Patent number: 10127624
    Abstract: An apparatus includes a central processing unit and a parallel processing unit. The parallel processing unit includes an array of software-configurable general purpose processors, a globally-shared memory, and a shared memory. Each of the software-configurable general purpose processors in the array of software-configurable general purpose processors has access to the globally-shared memory to execute one or more portions of at least one of (i) a decoding program, (ii) an encoding program, and (iii) an encoding and decoding program. The shared memory is accessible by the central processing unit to program the shared memory with a map array describing a position of block data in one or more associated arrays.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: November 13, 2018
    Assignee: Amazon Technologies, Inc.
    Inventors: Jeffrey K. Lassahn, Timothy B. Prins
  • SWEEP DEPENDENCY BASED GRAPHICS PROCESSING UNIT BLOCK SCHEDULING
    Publication number: 20170238002
    Abstract: An apparatus includes a central processing unit and a parallel processing unit. The parallel processing unit generally includes an array of software-configurable general purpose processors, a globally shared memory, and a shared memory. Each of the software-configurable general purpose processors in the array of software-configurable general purpose processors generally has access to the globally shared memory to execute one or more portions of a decoding program. The shared memory is accessible by the central processing unit to program the shared memory with a schedule describing which of the one or more portions of the decoding program are to be executed by each of the software-configurable general purpose processors.
    Type: Application
    Filed: May 3, 2017
    Publication date: August 17, 2017
    Inventors: Timothy B. Prins, Jeffrey K. Lassahn
  • Sweep dependency based graphics processing unit block scheduling
    Patent number: 9667985
    Abstract: An apparatus includes a central processing unit and a parallel processing unit. The parallel processing unit generally includes an array of software-configurable general purpose processors, a globally shared memory, and a shared memory. Each of the software-configurable general purpose processors in the array of software-configurable general purpose processors generally has access to the globally shared memory to execute one or more portions of a decoding program. The shared memory is accessible by the central processing unit to program the shared memory with a schedule describing which of the one or more portions of the decoding program are to be executed by each of the software-configurable general purpose processors.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: May 30, 2017
    Assignee: Amazon Technologies, Inc.
    Inventors: Timothy B. Prins, Jeffrey K. Lassahn
  • Sweep dependency based graphics processing unit block scheduling
    Patent number: 9172923
    Abstract: An apparatus includes a central processing unit and a parallel processing unit. The parallel processing unit generally includes an array of software-configurable general purpose processors, a globally shared memory, and a shared memory. Each of the software-configurable general purpose processors in the array of software-configurable general purpose processors generally has access to the globally shared memory to execute one or more portions of a decoding program. The shared memory is accessible by the central processing unit to program the shared memory with a schedule describing which of the one or more portions of the decoding program are to be executed by each of the software-configurable general purpose processors.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: October 27, 2015
    Assignee: Elemental Technologies, Inc.
    Inventors: Timothy B. Prins, Jeffrey K. Lassahn