Abstract: A system and method for generating simulated wiring connections between a semiconductor device and a carrier. The method comprises identifying a plurality of first factors and instances of each first factor relating to the semiconductor device and identifying a plurality of second factors and instances of each second factor relating to the carrier. The first and second factors are associated with each other on a one-to-one basis. A simulated wiring connection is generated between a first I/O terminal and a matching second I/O terminal, subject to an identified instance of each first factor of each first I/O terminal being correlated to an identified instance of the associated second factor of the matching second I/O terminal. A simulated wiring connection is generated between third I/O terminals located in a first region and fourth I/O terminals located in said second region.

Abstract: A system and method for generating simulated wiring connections between first I/O terminals of a semiconductor device and second I/O terminals of a carrier. The method comprises identifying a plurality of first factors and instances of each first factor relating to a semiconductor device and identifying a plurality of second factors and instances of each second factor relating to a carrier. The first and second factors are associated with each other on a one-to-one basis. The instances of each first factor are correlated to the instances of each associated second factor on a one-to-one basis. A simulated wiring connection automatically is generated between each first I/O terminal and a matching second I/O terminal, subject to an identified instance of each first factor of each first I/O terminal being correlated to an identified instance of the associated second factor of the matching second I/O terminal.

Abstract: A method, structure, and method of design relating an electrical structure that includes a metal voltage plane laminated to a dielectric substrate. A determination is made as to where to place an opening for venting gases generated during fabrication of the dielectric laminate. An identification is made of a problematic opening in the metal voltage plane that is above or below a corresponding metal signal line within the dielectric laminate, such that an image of a portion of the corresponding metal signal line projects across the problematic opening. An electrically conductive strip is positioned across the problematic opening, such that the strip includes the image. In fabrication, the dielectric substrate having the metal signal line therein is provided. The metal voltage plane is laminated to the dielectric substrate. The opening in the metal voltage plane is formed such that the strip is across the opening and includes the image.

Abstract: The invention relates generally to a method of power supply noise and signal integrity analysis for creating frequency-dependent electrical models particularly related to microelectronic packages. The method discloses creation of equivalent circuits for geometries encountered in a typical chip package, including how to partition the geometry into cells which are less then 1/20 the minimum wavelength (?) in size, and how to handle signal and power supply vias, signal wires, and power planes. The method also instructs how to assign values to each of the inductors, capacitors, resistors, and transmission lines in each equivalent circuit. The method further provides modeling of only those interactions which occur between adjacent cells.

Abstract: An electrical resistance determination method. Input to the method includes a description of at least one electrical network within a substrate. The description includes specification of a plurality of first ports on a first side of the substrate, and a plurality of second ports on a second side of the substrate, for each electrical network. All of the first ports are electrically isolated from one another. All of the second ports are electrically connected to a common voltage. A computer readable program code, which is executed by a processor of a computer system computes for a first electrical network of the at least one electrical network an electrical resistance between each first port and a port of the second ports. The computer code may also display a perspective plot of the computed electrical resistances as a bar oriented about normal to each first port.

Abstract: The present invention provides a redistribution package having an upper surface that includes contacts with reduced pitch that correspond, for example, to that of a Controlled Collapse Chip Connection (“C4”) structure formed on a chip, and a lower surface having contacts with increased pitch that correspond, for example, to a printed circuit board employing ball grid array (“BGA”) pads. A series of power, signal and ground conductors extend through the body of the redistribution package and interconnect the circuit board contacts to the chip contacts.

Abstract: An electrical resistance determination method. Input to the method includes a description of at least one electrical network within a substrate. The description includes specification of a plurality of first ports on a first side of the substrate, and a plurality of second ports on a second side of the substrate, for each electrical network. All of the first ports are electrically isolated from one another. All of the second ports are electrically connected to a common voltage. A computer readable program code, which is executed by a processor of a computer system computes for a first electrical network of the at least one electrical network an electrical resistance between each first port and a port of the second ports. The computer code may also display a perspective plot of the computed electrical resistances as a bar oriented about normal to each first port.

Abstract: An integrated circuit chip (104) having a contact layer (136) that includes a plurality of Vdd, Vddx, ground and I/O contacts (116, 120, 124, 128) arranged in a generally radial pattern having diagonal and major axis symmetry and generally defining four quadrants. An X-Y power grid (140) is located beneath the contact layer and includes metal layers (LM?) each having a plurality of wires (68) extending in one direction. The direction of the wires alternates from one metal layer to the next adjacent metal layer. A wiring layer (IM) is interposed between the contact layer and power grid layers to provide a well-behaved electrical transition between the generally radial Vdd, Vddx and ground contacts and the rectangular X-Y power grid. The interposed wiring layer includes concentric square rings of Vdd, Vddx and ground wires (144, 148, 152) located alternatingly with one another.