Patents by Inventor Timothy C. Krywanczyk
Timothy C. Krywanczyk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10192748Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a method to control depth of etch in deep via etching and related structures. The method includes: forming an interface within the substrate between an etch control dopant and material of the substrate; etching a via within substrate; and terminating the etching of the via at the interface upon detection of the interface.Type: GrantFiled: October 19, 2016Date of Patent: January 29, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Timothy C. Krywanczyk, Patrick A. Raymond, John C. Hall, Damyon L. Corbin
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Publication number: 20180108535Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a method to control depth of etch in deep via etching and related structures. The method includes: forming an interface within the substrate between an etch control dopant and material of the substrate; etching a via within substrate; and terminating the etching of the via at the interface upon detection of the interface.Type: ApplicationFiled: October 19, 2016Publication date: April 19, 2018Inventors: Timothy C. Krywanczyk, Patrick A. Raymond, John C. Hall, Damyon L. Corbin
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Patent number: 8806740Abstract: A silicon chicklet pedestal for use in a wafer-level test probe of a wafer is provided and includes a main body, first and second opposing faces, and an array of vias formed through the main body to extend between the first and second faces, through which pairs of leads, respectively associated with each via at the first and second faces, are electrically connectable to one another.Type: GrantFiled: April 28, 2011Date of Patent: August 19, 2014Assignee: International Business Machines CorporationInventors: S. Jay Chey, Timothy C. Krywanczyk, Mohammed S. Shaikh, Matthew T. Tiersch, Cornelia Kang-I Tsang
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Patent number: 8595919Abstract: A silicon chicklet pedestal for use in a wafer-level test probe of a wafer is provided and includes a main body, first and second opposing faces, and an array of vias formed through the main body to extend between the first and second faces, through which pairs of leads, respectively associated with each via at the first and second faces, are electrically connectable to one another.Type: GrantFiled: April 28, 2011Date of Patent: December 3, 2013Assignee: International Business Machines CorporationInventors: S. Jay Chey, Timothy C. Krywanczyk, Mohammed S. Shaikh, Matthew T. Tiersch, Cornelia Kang-I Tsang
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Patent number: 8163602Abstract: There is provided a UV energy curable tape comprising an adhesive material including a UV energy curable oligomer, a UV energy initiator, and a material which emits optical light when the tape composition is substantially fully cured. A semiconductor chip made using the tape is also provided.Type: GrantFiled: January 21, 2011Date of Patent: April 24, 2012Assignee: International Business Machines CorporationInventors: Timothy C. Krywanczyk, Donald W. Brouillette, Steven A. Martel, Matthew R. Whalen
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Patent number: 8034718Abstract: Disclosed are embodiments of a method of removing patterned circuit structures from the surface of a semiconductor wafer. The method embodiments comprise blasting the surface of the semiconductor wafer with particles so as to remove substantially all of the patterned circuit structures. The blasting process is followed by one or more grinding, polishing and/or cleaning processes to remove any remaining circuit structures, to remove any lattice damage and/or to achieve a desired smoothness across the surface of the semiconductor wafer.Type: GrantFiled: February 15, 2008Date of Patent: October 11, 2011Assignee: International Business Machines CorporationInventors: Steven R. Codding, David Domina, James L. Hardy, Jr., Timothy C. Krywanczyk
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Publication number: 20110199109Abstract: A silicon chicklet pedestal for use in a wafer-level test probe of a wafer is provided and includes a main body, first and second opposing faces, and an array of vias formed through the main body to extend between the first and second faces, through which pairs of leads, respectively associated with each via at the first and second faces, are electrically connectable to one another.Type: ApplicationFiled: April 28, 2011Publication date: August 18, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: S. Jay Chey, Timothy C. Krywanczyk, Mohammed S. Shaikh, Matthew T. Tiersch, Cornelia Tsang
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Publication number: 20110199108Abstract: A silicon chicklet pedestal for use in a wafer-level test probe of a wafer is provided and includes a main body, first and second opposing faces, and an array of vias formed through the main body to extend between the first and second faces, through which pairs of leads, respectively associated with each via at the first and second faces, are electrically connectable to one another.Type: ApplicationFiled: April 28, 2011Publication date: August 18, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: S. Jay Chey, Timothy C. Krywanczyk, Mohammed S. Shaikh, Matthew T. Tiersch, Cornelia Tsang
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Patent number: 7987591Abstract: A silicon chicklet pedestal for use in a wafer-level test probe of a wafer is provided and includes a main body, first and second opposing faces, and an array of vias formed through the main body to extend between the first and second faces, through which pairs of leads, respectively associated with each via at the first and second faces, are electrically connectable to one another.Type: GrantFiled: August 13, 2009Date of Patent: August 2, 2011Assignee: International Business Machines CorporationInventors: S. Jay Chey, Timothy C. Krywanczyk, Mohammed S. Shaikh, Matthew T. Tiersch, Cornelia Kang-I Tsang
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Publication number: 20110115072Abstract: There is provided a UV energy curable tape comprising an adhesive material including a UV energy curable oligomer, a UV energy initiator, and a material which emits optical light when the tape composition is substantially fully cured. A semiconductor chip made using the tape is also provided.Type: ApplicationFiled: January 21, 2011Publication date: May 19, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Timothy C. Krywanczyk, Donald W. Brouillette, Steven A. Martel, Matthew R. Whalen
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Patent number: 7932614Abstract: A C4 grind tape and a laser-ablative adhesive layer are formed on a front side of a semiconductor substrate. A carrier substrate is thereafter attached to the laser-ablative adhesive layer. The back side of the semiconductor substrate is thinned by polishing or grinding, during which the carrier substrate provides mechanical support to enable thinning of the semiconductor substrate to a thickness of about 25 ?m. A film frame tape is attached to the back side of the thinned semiconductor substrate and the laser-ablative adhesive layer is ablated by laser, thereby dissociating the carrier substrate from the back side of the C4 grind tape. The assembly of the film frame tape, the thinned semiconductor substrate, and the C4 grind tape is diced. The C4 grind tape is irradiated by ultraviolet light to become less adhesive, and is subsequently removed.Type: GrantFiled: October 21, 2010Date of Patent: April 26, 2011Assignee: International Business Machines CorporationInventors: Steven R. Codding, Timothy C. Krywanczyk, Timothy E. Neary, Edmund J. Sprogis
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Patent number: 7902682Abstract: There is provided a UV energy curable tape comprising an adhesive material including a UV energy curable oligomer, a UV energy initiator, and a material which emits optical light when the tape composition is substantially fully cured. A semiconductor chip made using the tape is also provided.Type: GrantFiled: November 18, 2003Date of Patent: March 8, 2011Assignee: International Business Machines CorporationInventors: Timothy C. Krywanczyk, Donald W. Brouillette, Steven A. Martel, Matthew R. Whalen
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Publication number: 20110037489Abstract: A silicon chicklet pedestal for use in a wafer-level test probe of a wafer is provided and includes a main body, first and second opposing faces, and an array of vias formed through the main body to extend between the first and second faces, through which pairs of leads, respectively associated with each via at the first and second faces, are electrically connectable to one another.Type: ApplicationFiled: August 13, 2009Publication date: February 17, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: S. Jay Chey, Timothy C. Krywanczyk, Mohammed S. Shaikh, Matthew T. Tiersch, Cornelia Tsang
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Publication number: 20110031620Abstract: A C4 grind tape and a laser-ablative adhesive layer are formed on a front side of a semiconductor substrate. A carrier substrate is thereafter attached to the laser-ablative adhesive layer. The back side of the semiconductor substrate is thinned by polishing or grinding, during which the carrier substrate provides mechanical support to enable thinning of the semiconductor substrate to a thickness of about 25 ?m. A film frame tape is attached to the back side of the thinned semiconductor substrate and the laser-ablative adhesive layer is ablated by laser, thereby dissociating the carrier substrate from the back side of the C4 grind tape. The assembly of the film frame tape, the thinned semiconductor substrate, and the C4 grind tape is diced. The C4 grind tape is irradiated by ultraviolet light to become less adhesive, and is subsequently removed.Type: ApplicationFiled: October 21, 2010Publication date: February 10, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Steven R. Codding, Timothy C. Krywanczyk, Timothy E. Neary, Edmund J. Sprogis
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Patent number: 7867876Abstract: A C4 grind tape and a laser-ablative adhesive layer are formed on a front side of a semiconductor substrate. A carrier substrate is thereafter attached to the laser-ablative adhesive layer. The back side of the semiconductor substrate is thinned by polishing or grinding, during which the carrier substrate provides mechanical support to enable thinning of the semiconductor substrate to a thickness of about 25 ?m. A film frame tape is attached to the back side of the thinned semiconductor substrate and the laser-ablative adhesive layer is ablated by laser, thereby dissociating the carrier substrate from the back side of the C4 grind tape. The assembly of the film frame tape, the thinned semiconductor substrate, and the C4 grind tape is diced. The C4 grind tape is irradiated by ultraviolet light to become less adhesive, and is subsequently removed.Type: GrantFiled: December 23, 2008Date of Patent: January 11, 2011Assignee: International Business Machines CorporationInventors: Steven R. Codding, Timothy C. Krywanczyk, Timothy E. Neary, Edmund J. Sprogis
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Patent number: 7855130Abstract: An improved method of dicing a semiconductor wafer which substantially reduces or eliminates corrosion of copper-containing, aluminum bonding pads. The method involves continuously contacting the bonding pads with deionized water and an effective amount of a copper corrosion inhibiting agent, most preferably benzotriazole. Also disclosed, is an improved apparatus for dicing a wafer, in which a copper corrosion inhibiting agent is included in the cooling system for cooling the dicing blade.Type: GrantFiled: April 21, 2003Date of Patent: December 21, 2010Assignee: International Business Machines CorporationInventors: Robert R Cadieux, Scott A Estes, Timothy C Krywanczyk
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Patent number: 7844099Abstract: A method for inspecting a semiconductor wafer fabricated for image sensing operation that has had a transparent protective tape layer applied to a front or active wafer surface. The method includes quantifying chip defects in the image sensor wafer that lie under the protective layer using automatic disposition equipment.Type: GrantFiled: November 15, 2006Date of Patent: November 30, 2010Assignee: International Business Machines CorporationInventors: Timothy C. Krywanczyk, Timothy E. Neary, Erik M. Probstfield
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Patent number: 7771560Abstract: A method for preventing edge chipping and cracking damage encountered by semiconductor chips in a die picking operation during separation from an adhesive sheet. Also provided is a device for preventing potential edge chipping and cracking damage encountered by a semiconductor chip during die picking processes.Type: GrantFiled: September 28, 2007Date of Patent: August 10, 2010Assignee: International Business Machines CorporationInventors: James R. Johnson, Timothy C. Krywanczyk, Matthew R. Whalen
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Publication number: 20100155936Abstract: A C4 grind tape and a laser-ablative adhesive layer are formed on a front side of a semiconductor substrate. A carrier substrate is thereafter attached to the laser-ablative adhesive layer. The back side of the semiconductor substrate is thinned by polishing or grinding, during which the carrier substrate provides mechanical support to enable thinning of the semiconductor substrate to a thickness of about 25 ?m. A film frame tape is attached to the back side of the thinned semiconductor substrate and the laser-ablative adhesive layer is ablated by laser, thereby dissociating the carrier substrate from the back side of the C4 grind tape. The assembly of the film frame tape, the thinned semiconductor substrate, and the C4 grind tape is diced. The C4 grind tape is irradiated by ultraviolet light to become less adhesive, and is subsequently removed.Type: ApplicationFiled: December 23, 2008Publication date: June 24, 2010Applicant: International Business Machines CorporationInventors: Steven R. Codding, Timothy C. Krywanczyk, Timothy E. Neary, Edmund J. Sprogis
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Patent number: 7722446Abstract: In accordance with the foregoing objects and advantages, the present invention provides a fabrication device that may be used during the grinding operation of the fabrication process. The fabrication device comprises a socket plate that includes a plurality of cavities formed therein that correspond in position and number to the solder (or other conductive material) bumps formed on the front surface of a product wafer.Type: GrantFiled: October 17, 2006Date of Patent: May 25, 2010Assignee: International Business Machines CorporationInventors: Timothy C Krywanczyk, Edmund J Sprogis