Abstract: The present disclosure describes an integrated opto-mechanical and electro-mechanical system. The opto-mechanical and electro-mechanical system can be made of photonic crystals configured to move based on electrical voltages and/or back action effects from electromagnetic waves, thus changing the resonance of the system.

Abstract: Systems and methods for implementing a zero overhead loop in a microprocessor or microprocessor based system/chip are disclosed. The systems and methods include the use of a breakpoint mechanism, and modification of parameters at runtime, with the breakpoint mechanism being additionally used in debugging, in order to provide some of the looping functionality.

Abstract: An embodiment of the present invention provides a system for implementing a Reed-Solomon computation of parity bytes of a codeword, including an accumulator and a logic circuit. The accumulator is configured to hold a plurality of bits. In an embodiment, each bit held in the accumulator initially corresponds to a bit associated with a data byte of the codeword. In another embodiment, each bit held in the accumulator initially correspond to a fixed value. The logic circuit is configured to iteratively compute a new bit for each bit held in the accumulator. After a last iteration of the computation, the bits held in the accumulator correspond to the parity bytes, wherein for each bit held in the accumulator each iteration of the computation comprises computing an exclusive-OR of a fixed subset of bits held in the accumulator. In an embodiment, the exclusive-OR is computed for the fixed subset of bits held in the accumulator and an input bit of the codeword.

Abstract: An embodiment of the present invention provides a system for implementing a Reed-Solomon computation of parity bytes of a codeword, including an accumulator and a logic circuit. The accumulator is configured to hold a plurality of bits. In an embodiment, each bit held in the accumulator initially corresponds to a bit associated with a data byte of the codeword. In another embodiment, each bit held in the accumulator initially correspond to a fixed value. The logic circuit is configured to iteratively compute a new bit for each bit held in the accumulator. After a last iteration of the computation, the bits held in the accumulator correspond to the parity bytes, wherein for each bit held in the accumulator each iteration of the computation comprises computing an exclusive-OR of a fixed subset of bits held in the accumulator. In an embodiment, the exclusive-OR is computed for the fixed subset of bits held in the accumulator and an input bit of the codeword.

Abstract: A method is used that substantially simultaneously trellis encodes data to be modulated onto multiple tones. The embodiments of the present invention comprise the steps of: (a) using a first input operand comprising state bits for a first trellis stage; (b) using a second input operand comprising a plurality of input data bits; and (c) generating an output comprising output data bits and output state bits from a first or later trellis stage.

Abstract: There is disclosed a technique for accessing a register file which comprises defining a first register address as a plurality of bits and using said first register address to access said register file generating a second register address by using a sequence of said plurality of bits with at least one of said plurality of bits supplied via a unitary operator, the unitary operator being effective to selectively alter the logical value of said bit depending on its logical value in the first register address, and using said second register address to access said register file. A computer system for carrying out such a technique is also enclosed.

Abstract: A method and apparatus are disclosed for efficiently de-scrambling one or more bytes of data according to DSL standards on a processor. This is achieved by providing an instruction for de-scrambling one or more bytes of data according to the DSL standards. Accordingly, the invention advantageously provides a processor with the ability to de-scramble data with a single instruction thus allowing for more efficient and faster de-scrambling operations for subsequent processing.

Abstract: A method and apparatus are disclosed for efficiently de-scrambling and bit-order-reversing one or more bytes of data according to DSL standards on a processor. In a preferred embodiment, this is achieved by providing an instruction for de-scrambling and bit-order-reversing one or more bytes of data according to DSL standards. Accordingly, the invention advantageously provides a processor with the ability to de-scramble and bit-order-reverse data with a single instruction thus allowing for more efficient and faster de-scrambling operations for subsequent processing.

Abstract: An execution unit and a new set of instructions for performing Viterbi decoding are provided. The instructions can be built into an execution unit which executes other instructions, or in their own execution unit. In an example implementation, the new set of instructions are used in implementing a modem for a high bit rate single-pair high speed digital subscriber line (“SHDSL”) system. In the example implementation, the execution unit includes registers to hold the input metrics, so the same metrics do not need to be supplied for each instruction that uses them. The execution unit also includes registers to accumulate decision values, so that as many can be retrieved at once as makes best use of the data path out of the execution unit. The instructions may employ modulo arithmetic to avoid the necessity to rescale the state metrics.

Abstract: In an Asynchronous Transfer Mode cell, a method and apparatus are disclosed for producing a cell header having bytes with bits in reverse order. Address and control data bytes are received, and a value for a reverse bit Header Error Control byte is generated from the address and control data bytes. Additionally, the order of bits within each address and control data byte is reversed. The produced cell header comprises the reverse bit Header Error Control byte and the address and control data bytes with each address and control data byte having its bits in reversed order. In one embodiment, the present invention provides a processor instruction for producing the cell header having bytes with bits in reverse order. The instruction receives as input address and control data bytes. The instruction then computes a Header Error Control byte and formats the Header Error Control byte in reverse bit order for subsequent processing within the modem.

Abstract: A method and apparatus are disclosed for efficiently scrambling one or more bytes of data according to DSL standards on a processor. This is achieved by providing an instruction for scrambling one or more bytes of data according to the DSL standards. Accordingly, the invention advantageously provides a processor with the ability to scramble data with a single instruction thus allowing for more efficient and faster scrambling operations for subsequent modulation and transmission.

Abstract: An execution unit and method for performing Viterbi decoding is provided. The instruction may be built into an execution unit which executes other instructions, or in its own execution unit. In an example implementation, the instruction is used in implementing the central-office modem (ATU-C) of an asymmetric digital subscriber line (“ADSL”) system. In the example implementation, the new instruction takes as input eight input metrics and eight state metrics, and returns as output eight updated state metrics and eight decision bytes. The decision bytes contain: two ‘path’ bits to enable the previous state to be quickly identified; bits to enable the input bits to be quickly identified; and a carry bit to allow the full value of a state metric to be reconstructed, even though during the calculation only the bottom bits are calculated.

Abstract: A transmitter unit for transmitting data via a data link is described, wherein the transmitter unit comprises a header compression unit adapted for converting a primary header of a data packet to be transmitted into a corresponding secondary header, with said primary header being related to said secondary header in one-to-one correspondence. The transmitter unit is adapted for transmitting a modified data packet via said data link, said modified data packet comprising the corresponding secondary header. Furthermore, a receiver unit for receiving data transmitted via a data link is described. The receiver unit comprises a header decompression unit adapted for converting a secondary header of a modified data packet received via said data link into a corresponding primary header.