Patents by Inventor Timothy E. Dearden

Timothy E. Dearden has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7888176
    Abstract: In one or more embodiments, a method of producing a stacked integrated circuit assembly includes providing a substrate having a top surface with at least one substrate connection pad. A first flip chip integrated circuit (FFIC) is disposed above the substrate, and a second flip chip integrated circuit (SFIC) is disposed above the FFIC. The FFIC may be disposed between the substrate and the SFIC. The method includes making at least one solder connection between the substrate connection pad and the FFIC and at least one solder connection between the FFIC and the SFIC.
    Type: Grant
    Filed: September 10, 2009
    Date of Patent: February 15, 2011
    Assignee: Raytheon Company
    Inventors: Tse E. Wong, Samuel D. Tonomura, Stephen E. Sox, Timothy E. Dearden, Clifton Quan, Polwin C. Chan, Mark S. Hauhe
  • Publication number: 20100003785
    Abstract: In one or more embodiments, a method of producing a stacked integrated circuit assembly includes providing a substrate having a top surface with at least one substrate connection pad. A first flip chip integrated circuit (FFIC) is disposed above the substrate, and a second flip chip integrated circuit (SFIC) is disposed above the FFIC. The FFIC may be disposed between the substrate and the SFIC. The method includes making at least one solder connection between the substrate connection pad and the FFIC and at least one solder connection between the FFIC and the SFIC.
    Type: Application
    Filed: September 10, 2009
    Publication date: January 7, 2010
    Applicant: RAYTHEON COMPANY
    Inventors: Tse E. WONG, Samuel D. TONOMURA, Stephen E. SOX, Timothy E. DEARDEN, Clifton QUAN, Polwin C. CHAN, Mark S. HAUHE
  • Patent number: 7605477
    Abstract: A stacked integrated circuit assembly includes a substrate having a top surface with at least one substrate connection pad. A first flip chip integrated circuit (FFIC) is disposed above the substrate, and a second flip chip integrated circuit (SFIC) is disposed above the FFIC. The FFIC is disposed between the substrate and the SFIC. The stacked integrated circuit assembly includes least one solder connection between the substrate connection pad and the FFIC and at least one solder connection between the FFIC and the SFIC.
    Type: Grant
    Filed: January 25, 2007
    Date of Patent: October 20, 2009
    Assignee: Raytheon Company
    Inventors: Tse E. Wong, Samuel D. Tonomura, Stephen E. Sox, Timothy E. Dearden, Clifton Quan, Polwin C. Chan, Mark S. Hauhe
  • Publication number: 20080179758
    Abstract: A stacked integrated circuit assembly includes a substrate having a top surface with at least one substrate connection pad. A first flip chip integrated circuit (FFIC) is disposed above the substrate, and a second flip chip integrated circuit (SFIC) is disposed above the FFIC. The FFIC is disposed between the substrate and the SFIC. The stacked integrated circuit assembly includes least one solder connection between the substrate connection pad and the FFIC and at least one solder connection between the FFIC and the SFIC.
    Type: Application
    Filed: January 25, 2007
    Publication date: July 31, 2008
    Inventors: Tse E. Wong, Samuel D. Tonomura, Stephen E. Sox, Timothy E. Dearden, Clifton Quan, Polwin C. Chan, Mark S. Hauhe
  • Patent number: 6417747
    Abstract: An RF interconnect is incorporated in RF module packages for direct attachment onto a multi-layer PWB using compressible center conductor (fuzz button) interconnects. The module has circuitry operating at microwave frequencies. The module package includes a metal housing including a metal bottom wall structure. The module includes a plurality of RF interconnects, which provide RF interconnection between the package and the PWB. Each interconnect includes a feedthrough center pin protruding through an opening formed in the metal bottom wall, with isolation provided by a dielectric feedthrough insulator. The center pin is surrounded with a ring of shield pins attached to the external surface of the bottom wall of the module housing. The pins are insertable in holes formed in the PWB, and make contact with fuzz button interconnects disposed in the holes. Circuitry connects the fuzz button interconnects to appropriate levels of the PWB for grounding and RF signal conduction.
    Type: Grant
    Filed: August 23, 2001
    Date of Patent: July 9, 2002
    Assignee: Raytheon Company
    Inventors: Timothy E. Dearden, Jeffrey J. Stitt, Clifton Quan
  • Patent number: 4866837
    Abstract: An assembly station (10) is used to align termini or leads of components (16) with attachment pads on circuit boards (20) to enable the component and circuit board pads to be precisely aligned and coupled together. A dual port probe (22), which is secured to an x-y table, is provided with upper and lower viewing ports (30, 32) which respectively view the component and the circuit board. Images from the two are directed to video cameras (34, 36) and the signals therefrom are processed by a vision system (38) which compares the alignment of the pads and provides error correction signals (x, y, .theta.) to a robotic arm (12) to move component (16) and its pad or termini into alignment with the pads on the circuit board. Thereafter, the robotic arm brings the component into contact with the circuit board for soldering of the respective leads together.
    Type: Grant
    Filed: December 3, 1987
    Date of Patent: September 19, 1989
    Assignee: Hughes Aircraft Company
    Inventors: Gail M. Heissenberger, Timothy E. Dearden, David M. Zehnpfennig