Abstract: An apparatus, includes an interconnect, including a conductive material, above a substrate and a resistive random access memory (RRAM) device coupled to the interconnect. The RRAM device includes an electrode structure above the interconnect, where an upper portion of the electrode structure has a first width. The RRAM device further includes a switching layer on the electrode structure, where the switching layer has the first width and an oxygen exchange layer, having a second width less than the first width, on a portion of the switching layer. The RRAM device further includes a top electrode above the oxygen exchange layer, where the top electrode has the second width and an encapsulation layer on a portion of the switching layer, where the switching layer extends along a sidewall of the oxygen exchange layer.

Abstract: Approaches for fabricating RRAM stacks with reduced forming voltage, and the resulting structures and devices, are described. In an example, a resistive random access memory (RRAM) device includes a conductive interconnect in an inter-layer dielectric (ILD) layer above a substrate. An RRAM element is on the conductive interconnect, the RRAM element including a first electrode layer on the uppermost surface of the conductive interconnect. A resistance switching layer is on the first electrode layer, the resistance switching layer including a first metal oxide material layer on the first electrode layer, and a second metal oxide material layer on the first metal oxide material layer, the second metal oxide material layer including a metal species not included in the first metal oxide material layer. An oxygen exchange layer is on the second metal oxide material layer of the resistance switching layer. A second electrode layer is on the oxygen exchange layer.

Abstract: An apparatus, includes an interconnect, including a conductive material, above a substrate and a resistive random access memory (RRAM) device coupled to the interconnect. The RRAM device includes an electrode structure above the interconnect, where an upper portion of the electrode structure has a first width. The RRAM device further includes a switching layer on the electrode structure, where the switching layer has the first width and an oxygen exchange layer, having a second width less than the first width, on a portion of the switching layer. The RRAM device further includes a top electrode above the oxygen exchange layer, where the top electrode has the second width and an encapsulation layer on a portion of the switching layer, where the switching layer extends along a sidewall of the oxygen exchange layer.

Abstract: Approaches for fabricating RRAM stacks with reduced forming voltage, and the resulting structures and devices, are described. In an example, a resistive random access memory (RRAM) device includes a conductive interconnect in an inter-layer dielectric (ILD) layer above a substrate. An RRAM element is on the conductive interconnect, the RRAM element including a first electrode layer on the uppermost surface of the conductive interconnect. A resistance switching layer is on the first electrode layer, the resistance switching layer including a first metal oxide material layer on the first electrode layer, and a second metal oxide material layer on the first metal oxide material layer, the second metal oxide material layer including a metal species not included in the first metal oxide material layer. An oxygen exchange layer is on the second metal oxide material layer of the resistance switching layer. A second electrode layer is on the oxygen exchange layer.

Abstract: Bottom-up fill approaches for forming metal features of semiconductor structures, and the resulting structures, are described. In an example, a semiconductor structure includes a trench disposed in an inter-layer dielectric (ILD) layer. The trench has sidewalls, a bottom and a top. A U-shaped metal seed layer is disposed at the bottom of the trench and along the sidewalls of the trench but substantially below the top of the trench. A metal fill layer is disposed on the U-shaped metal seed layer and fills the trench to the top of the trench. The metal fill layer is in direct contact with dielectric material of the ILD layer along portions of the sidewalls of the trench above the U-shaped metal seed layer.

Abstract: Metal-insulator-metal (MIM) capacitors with insulator stacks having a plurality of metal oxide layers are described. For example, a MIM capacitor for a semiconductor device includes a trench disposed in a dielectric layer disposed above a substrate. A first metal plate is disposed along the bottom and sidewalls of the trench. An insulator stack is disposed above and conformal with the first metal plate. The insulator stack includes a first metal oxide layer having a first dielectric constant and a second metal oxide layer having a second dielectric constant. The first dielectric constant is higher than the second dielectric constant. The MIM capacitor also includes a second metal plate disposed above and conformal with the insulator stack.

Abstract: Atomic layer deposition (ALD) of TaAlC for capacitor integration is generally described. For example, a semiconductor structure includes a plurality of semiconductor devices disposed in or above a substrate. One or more dielectric layers are disposed above the plurality of semiconductor devices. A metal-insulator-metal (MIM) capacitor is disposed in at least one of the dielectric layers, the MIM capacitor includes an electrode having a conformal layer of TaAlC and the MIM capacitor is electrically coupled to one or more of the semiconductor devices. Other embodiments are also disclosed and claimed.

Abstract: Metal-insulator-metal (MIM) capacitors with insulator stacks having a plurality of metal oxide layers are described. For example, a MIM capacitor for a semiconductor device includes a trench disposed in a dielectric layer disposed above a substrate. A first metal plate is disposed along the bottom and sidewalls of the trench. An insulator stack is disposed above and conformal with the first metal plate. The insulator stack includes a first metal oxide layer having a first dielectric constant and a second metal oxide layer having a second dielectric constant. The first dielectric constant is higher than the second dielectric constant. The MIM capacitor also includes a second metal plate disposed above and conformal with the insulator stack.

Abstract: Methods to form memory devices having a MIM capacitor with a recessed electrode are described. In one embodiment, a method of forming a MIM capacitor with a recessed electrode includes forming an excavated feature defined by a lower portion that forms a bottom and an upper portion that forms sidewalls of the excavated feature. The method includes depositing a lower electrode layer in the feature, depositing an electrically insulating layer on the lower electrode layer, and depositing an upper electrode layer on the electrically insulating layer to form the MIM capacitor. The method includes removing an upper portion of the MIM capacitor to expose an upper surface of the electrode layers and then selectively etching one of the electrode layers to recess one of the electrode layers. This recess isolates the electrodes from each other and reduces the likelihood of a current leakage path between the electrodes.

Abstract: A ?-diketonate alkoxide metal compound and a source reagent composition are provided. The ?-diketonate alkoxide metal compound may include a metal M selected from Mg, Ca, Sr, Ba, Sc, Y, La, Ce, Ti, Zr, Hf, Pr, V, Nb, Ta, Nd, Cr, W, Pm, Mn, Re, Sm, Fe, Ru, Eu, Co, Rh, Ir, Gd, Ni, Tb, Cu, Dy, Ho, Al, Tl, Er, Sn, Pb, Tm, Bi, Lu, Th, Pd, Pt, Ga, In, Au, Ag, Li, Na, K, Rb, Cs, Mo, and Yb. The metal may be complexed to at least one alkoxide ligand and one ?-diketonate ligand.

Abstract: A metalorganic complex composition comprising a metalorganic complex selected from the group consisting of: metalorganic complexes comprising one or more metal central atoms coordinated to one or more monodentate or multidentate organic ligands, and complexed with one or more complexing monodentate or multidentate ligands containing one or more atoms independently selected from the group consisting of atoms of the elements C, N, H, S, O and F; wherein when the number of metal atoms is one and concurrently the number of complexing monodentate or multidentate ligands is one, then the complexing monodentate or multidentate ligand of the metalorganic complex is selected from the group consisting of beta-ketoiminates, beta-diiminates, C2-C10 alkenyl, C2-C15 cycloalkenyl and C6-C10 aryl.

Abstract: A semiconductor device comprises a substrate, a channel region, and a gate formed in association with the channel region. In one exemplary embodiment, the gate comprises a first material that is formed void free on an interior surface of a gate trench of the gate. A width of the gate trench comprises between about 8 nm and about 65 nm. The gate comprises a transition metal alloyed with carbon, aluminum or nitrogen, or combinations thereof, to form a carbide, a nitride, or a carbo-nitride, or combinations thereof, of the transition metal. In another exemplary embodiment, the gate further comprises a second material formed void free on an interior surface of the first material and comprises a transition metal alloyed with carbon, aluminum or nitrogen, or combinations thereof, to form a carbide, a nitride, or a carbo-nitride, or combinations thereof, of the transition metal.

Abstract: Methods to form memory devices having a MIM capacitor with a recessed electrode are described. In one embodiment, a method of forming a MIM capacitor with a recessed electrode includes forming an excavated feature defined by a lower portion that forms a bottom and an upper portion that forms sidewalls of the excavated feature. The method includes depositing a lower electrode layer in the feature, depositing an electrically insulating layer on the lower electrode layer, and depositing an upper electrode layer on the electrically insulating layer to form the MIM capacitor. The method includes removing an upper portion of the MIM capacitor to expose an upper surface of the electrode layers and then selectively etching one of the electrode layers to recess one of the electrode layers. This recess isolates the electrodes from each other and reduces the likelihood of a current leakage path between the electrodes.

Abstract: A metalorganic complex composition comprising a metalorganic complex selected from the group consisting of: metalorganic complexes comprising one or more metal central atoms coordinated to one or more monodentate or multidentate organic ligands, and complexed with one or more complexing monodentate or multidentate ligands containing one or more atoms independently selected from the group consisting of atoms of the elements C, N, H, S, O and F; wherein when the number of metal atoms is one and concurrently the number of complexing monodentate or multidentate ligands is one, then the complexing monodentate or multidentate ligand of the metalorganic complex is selected from the group consisting of beta-ketoiminates, beta-diiminates, C2-C10 alkenyl, C2-C15 cycloalkenyl and C6-C10 aryl.

Abstract: A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer on a substrate. After removing impurities from that layer, and increasing its oxygen content, a gate electrode is formed on the high-k gate dielectric layer.

Abstract: A method for making a semiconductor device is described. That method comprises forming on a substrate a buffer layer and a high-k gate dielectric layer, oxidizing the surface of the high-k gate dielectric layer, and then forming a gate electrode on the oxidized high-k gate dielectric layer.

Abstract: A method for making a semiconductor device is described. That method comprises forming on a substrate a buffer layer and a high-k gate dielectric layer, oxidizing the surface of the high-k gate dielectric layer, and then forming a gate electrode on the oxidized high-k gate dielectric layer.

Abstract: A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer on a substrate. After removing impurities from that layer, and increasing its oxygen content, a gate electrode is formed on the high-k gate dielectric layer.

Abstract: A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer on a substrate. After forming a silicon nitride layer on the high-k gate dielectric layer, a gate electrode is formed on the silicon nitride layer.

Abstract: A method of forming on a substrate a metal film, comprising depositing said metal film on said substrate via chemical vapor deposition from a metalorganic complex of the formula:MA.sub.Y Xwherein:M is a y-valent metal;A is a monodentate or multidentate organic ligand coordinated to M which allows complexing of MA.sub.y with X;y is an integer having a value of 2, 3 or 4; each of the A ligands may be the same or different; andX is a monodentate or multidentate ligand coordinated to M and containing one or more atoms independently selected from the group consisting of atoms of the elements C, N, H, S, O and F.The metal M may be selected from the group consisting of Cu, Ba, Sr, La, Nd, Ce, Pr, Sm, Eu, Th, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Bi, Tl, Y, Pb, Ni, Pd, Pt, Al, Ga, In, Ag, Au, Co, Rh, Ir, Fe, Ru, Sn, Li, Na, K, Rb, Cs, Ca, Mg, Ti, Zr, Hf, V, Nb, Ta, Cr, Mo, and W. A may be selected from the group consisting of .beta.-diketonates, .beta.