Abstract: On data writes to a cache memory in a digital data processing system, the existing data currently stored on the desired cache storage line is read out and parity checked. The read-out data is modified with new data only if there is no parity error. If a parity error is detected, a cache miss is signaled and the read-out line of data is written back into the cache memory with error correction code checking and error correction being performed on the defective line of data as part of this write-back to the cache memory.

Abstract: A data processing system including an addressable main memory for storing data and directly executable microinstructions, and a central processing chip having a data interface terminal and an instruction terminal. A processor memory bus is connected between the main addressable memory and the central processing chip data interface terminal. An instruction bus is connected between the central processing chip instruction terminal and the addressable memory.The directly executable microinstructions in the addressable main memory are fetched from the main memory by an apparatus which includes an instruction address circuit connected to the processor memory bus and the instruction bus. The instruction address circuit includes a virtual address register circuit for receiving a portion of a virtual address from the instruction bus, and a portion of the mentioned virtual address from the processor memory bus.

Abstract: An error detection and correction apparatus including a transmission bus for transmitting multi-bit data signals and multi-bit error correction code signals generated responsive to the multi-bit data signals in accordance with a modified Hamming code technique. Parity generators are connected to the bus for receiving the bits of the data signals and selected bits of the error correction code signals in accordance with the modified Hamming code technique for determining if a single bit error exists in the data. A two-state comparison gate is connected to the parity generators which has a first state if a single bit error does exist, and a second state if a single bit error does not exist. A separate error detection and correction circuit is provided to detect and correct any single bit errors in the data on the transmission bus. The two-state comparison gate is reset to its second state after the separate error detection and correction circuit corrects any single bit error in the data.