Patents by Inventor Timothy G. McNamara
Timothy G. McNamara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10078418Abstract: In an approach for updating instructions of machine repairs to a user interface, a processor populates a quantity of machine components used to construct a machine model. A processor receives the machine model constructed from the quantity of machine components. A processor couples the machine model with a set of vital product data. A processor associates a set of instructions for a repair procedure with the machine model and the vital product data file. A processor generates a visual representation of the repair procedure specific to the machine model.Type: GrantFiled: December 20, 2016Date of Patent: September 18, 2018Assignee: International Business Machines CorporationInventors: An Ding Chen, Timothy G. McNamara
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Patent number: 10078970Abstract: In an approach for updating instructions of machine repairs to a user interface, a processor populates a quantity of machine components used to construct a machine model. A processor receives the machine model constructed from the quantity of machine components. A processor couples the machine model with a set of vital product data. A processor associates a set of instructions for a repair procedure with the machine model and the vital product data file. A processor generates a visual representation of the repair procedure specific to the machine model.Type: GrantFiled: December 20, 2016Date of Patent: September 18, 2018Assignee: International Business Machines CorporationInventors: An Ding Chen, Timothy G. McNamara
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Patent number: 9679411Abstract: In an approach for updating instructions of machine repairs to a user interface, a processor populates a quantity of machine components used to construct a machine model. A processor receives the machine model constructed from the quantity of machine components. A processor couples the machine model with a set of vital product data. A processor associates a set of instructions for a repair procedure with the machine model and the vital product data file. A processor generates a visual representation of the repair procedure specific to the machine model.Type: GrantFiled: December 19, 2014Date of Patent: June 13, 2017Assignee: International Business Machines CorporationInventors: An Ding Chen, Timothy G. McNamara
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Publication number: 20170092149Abstract: In an approach for updating instructions of machine repairs to a user interface, a processor populates a quantity of machine components used to construct a machine model. A processor receives the machine model constructed from the quantity of machine components. A processor couples the machine model with a set of vital product data. A processor associates a set of instructions for a repair procedure with the machine model and the vital product data file. A processor generates a visual representation of the repair procedure specific to the machine model.Type: ApplicationFiled: December 20, 2016Publication date: March 30, 2017Inventors: An Ding Chen, Timothy G. McNamara
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Publication number: 20170090717Abstract: In an approach for updating instructions of machine repairs to a user interface, a processor populates a quantity of machine components used to construct a machine model. A processor receives the machine model constructed from the quantity of machine components. A processor couples the machine model with a set of vital product data. A processor associates a set of instructions for a repair procedure with the machine model and the vital product data file. A processor generates a visual representation of the repair procedure specific to the machine model.Type: ApplicationFiled: December 20, 2016Publication date: March 30, 2017Inventors: An Ding Chen, Timothy G. McNamara
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Patent number: 9569889Abstract: In an approach for updating instructions of machine repairs to a user interface, a processor populates a quantity of machine components used to construct a machine model. A processor receives the machine model constructed from the quantity of machine components. A processor couples the machine model with a set of vital product data. A processor associates a set of instructions for a repair procedure with the machine model and the vital product data file. A processor generates a visual representation of the repair procedure specific to the machine model.Type: GrantFiled: April 27, 2016Date of Patent: February 14, 2017Assignee: International Business Machines CorporationInventors: An Ding Chen, Timothy G. McNamara
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Publication number: 20160225185Abstract: In an approach for updating instructions of machine repairs to a user interface, a processor populates a quantity of machine components used to construct a machine model. A processor receives the machine model constructed from the quantity of machine components. A processor couples the machine model with a set of vital product data. A processor associates a set of instructions for a repair procedure with the machine model and the vital product data file. A processor generates a visual representation of the repair procedure specific to the machine model.Type: ApplicationFiled: April 27, 2016Publication date: August 4, 2016Inventors: An Ding Chen, Timothy G. McNamara
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Publication number: 20160180015Abstract: In an approach for updating instructions of machine repairs to a user interface, a processor populates a quantity of machine components used to construct a machine model. A processor receives the machine model constructed from the quantity of machine components. A processor couples the machine model with a set of vital product data. A processor associates a set of instructions for a repair procedure with the machine model and the vital product data file. A processor generates a visual representation of the repair procedure specific to the machine model.Type: ApplicationFiled: December 19, 2014Publication date: June 23, 2016Inventors: Chen An Ding, Timothy G. McNamara
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Patent number: 8295419Abstract: A clock generator circuit for generating synchronization signals for a multiple chip system. The clock generator circuit comprises generation of a synchronization signal from a reference clock and chip global clock with edge detection logic. In high performance server system design with multiple chips, a common practice for server systems is to use feedback clock and delayed reference clock to generate the synchronization signal. The generated synchronization signal is transferred to latches clocked by the global clock to be used for chip synchronization functions. As the system clock frequency is pushed higher, the phase difference between generated synchronization signal clocked by feedback clock and receiving latch clocked by global clock is becoming such a large portion of cycle time that this signal cannot be transferred deterministically.Type: GrantFiled: October 18, 2010Date of Patent: October 23, 2012Assignee: International Business Machines CorporationInventors: Charlie C. Hwang, Wiren D. Becker, Timothy G. McNamara, Ching-Lung Tong
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Patent number: 7996715Abstract: A new multi nodal computer system comprising a number of nodes on which chips of different types reside. The new multi nodal computer system is characterized in that there is one clock chip per node, each clock chip controlling only the chips residing on that node said chips being appropriate for sending a check stop request to the associated clock chip in case of a malfunction. A new check stop handling method is characterized in that depending on the source of the check stop request the clock chip that received the check stop request initiates a system check stop, a node check up, or a chip check stop.Type: GrantFiled: November 5, 2008Date of Patent: August 9, 2011Assignee: International Business Machines CorporationInventors: Karin Rebmann, Dietmar Schmunkamp, Tobias Webel, Thomas E. Gilbert, Timothy G. McNamara, Patrick J. Meaney
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Publication number: 20110033017Abstract: A clock generator circuit for generating synchronization signals for a multiple chip system. The clock generator circuit comprises generation of a synchronization signal from a reference clock and chip global clock with edge detection logic. In high performance server system design with multiple chips, a common practice for server systems is to use feedback clock and delayed reference clock to generate the synchronization signal. The generated synchronization signal is transferred to latches clocked by the global clock to be used for chip synchronization functions. As the system clock frequency is pushed higher, the phase difference between generated synchronization signal clocked by feedback clock and receiving latch clocked by global clock is becoming such a large portion of cycle time that this signal cannot be transferred deterministically.Type: ApplicationFiled: October 18, 2010Publication date: February 10, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Charlie C. Hwang, Wiren D. Becker, Timothy G. McNamara, Ching-Lung Tong
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Patent number: 7826579Abstract: A clock generator circuit for generating synchronization signals for a multiple chip system. The clock generator circuit comprises generation of a synchronization signal from a reference clock and chip global clock with edge detection logic. In high performance server system design with multiple chips, a common practice for server systems is to use feedback clock and delayed reference clock to generate the synchronization signal. The generated synchronization signal is transferred to latches clocked by the global clock to be used for chip synchronization functions. As the system clock frequency is pushed higher, the phase difference between generated synchronization signal clocked by feedback clock and receiving latch clocked by global clock is becoming such a large portion of cycle time that this signal cannot be transferred deterministically.Type: GrantFiled: February 28, 2006Date of Patent: November 2, 2010Assignee: International Business Machines CorporationInventors: Charlie C. Hwang, Wiren D. Becker, Timothy G. McNamara, Ching-Lung Tong
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Publication number: 20090070622Abstract: A new multi nodal computer system comprising a number of nodes on which chips of different types reside. The new multi nodal computer system is characterized in that there is one clock chip per node, each clock chip controlling only the chips residing on that node said chips being appropriate for sending a check stop request to the associated clock chip in case of a malfunction. A new check stop handling method is characterized in that depending on the source of the check stop request the clock chip that received the check stop request initiates a system check stop, a node check up, or a chip check stop.Type: ApplicationFiled: November 5, 2008Publication date: March 12, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Karin Rebmann, Dietmar Schmunkamp, Tobias Webel, Thomas E. Gilbert, Timothy G. McNamara, Patrick J. Meaney
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Patent number: 7484118Abstract: The present invention provides a new multi nodal computer system comprising a number of nodes on which chips of different types reside. The new multi nodal computer system is characterized in that there is one clock chip per node, each clock chip controlling only the chips residing on that node said chips being appropriate for sending a check stop request to the associated clock chip in case of a malfunction. A new check stop handling method is characterized in that depending on the source of the check stop request the clock chip that received the check stop request initiates a system check stop, a node check up, or a chip check stop.Type: GrantFiled: December 16, 2004Date of Patent: January 27, 2009Assignee: International Business Machines CorporationInventors: Karin Rebmann, Dietmar Schmunkamp, Tobias Webel, Thomas E. Gilbert, Timothy G. McNamara, Patrick J. Meaney
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Patent number: 7437637Abstract: An apparatus and method for allowing for dynamic wordline repair in a clock running system in addition to allowing for programmable fuse support of combined Array Built-In Self-Test (ABIST) and Logic Built-In Self-Test (LBIST) testing. The method makes use of programmable fuses which contain Level Sensitive Scan Design (LSSD) latches which also have a system port. The system port allows for simpler reading of the fuses as well as for the dynamic updates of the programmable fuses for wordline and other repairs.Type: GrantFiled: January 20, 2006Date of Patent: October 14, 2008Assignee: International Business Machines CorporationInventors: Patrick J. Meaney, Timothy G. McNamara, Bryan L. Mechtly
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Publication number: 20080191753Abstract: A method for locally generating a ratio clock on a chip includes generating a global clock signal having a global clock cycle. A centralized state machine includes a counter going through a complete cycle in response to a non-integer number of global clock cycles, the state machine generating a control signal in response to the counter. The control signal is provided to staging latches, the staging latches generating a clock high signal and a clock low signal. Local pass gates generate an (n+0.5)-to-1 clock signal in response to the global clock signal, the clock high signal and the clock low signal.Type: ApplicationFiled: April 21, 2008Publication date: August 14, 2008Applicant: INTERNATIONAL BUSINESS MACHINE CORPORATIONInventors: William V. Huott, Charlie C. Hwang, Timothy G. McNamara
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Patent number: 7382844Abstract: A method of self-synchronizing clocks in a multiple chip system, by assigning one chip as the master chip and the other chips as slave chips. A training signal is sent from master chip to the slave chips to determine the latency from the master chip to a slave chip, and then a synchronization signal is sent out to synchronize the “time zero” of the chips.Type: GrantFiled: February 11, 2005Date of Patent: June 3, 2008Assignee: International Business Machines CorporationInventors: Charlie C. Hwang, Timothy G. McNamara, Ching-Lung Tong, Wiren Dale Becker
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Patent number: 7368958Abstract: A method for locally generating a ratio clock on a chip includes generating a global clock signal having a global clock cycle. A centralized state machine includes a counter going through a complete cycle in response to a non-integer number of global clock cycles, the state machine generating a control signal in response to the counter. The control signal is provided to staging latches, the staging latches generating a clock high signal and a clock low signal. Local pass gates generate an (n+0.5)-to-1 clock signal in response to the global clock signal, the clock high signal and the clock low signal.Type: GrantFiled: May 19, 2006Date of Patent: May 6, 2008Assignee: International Business Machines CorporationInventors: William V. Huott, Charlie C. Hwang, Timothy G. McNamara
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Patent number: 7355460Abstract: A method for locally generating a ratio clock on a chip includes generating a global clock signal having a global clock cycle. A centralized state machine is provided that includes a counter going through a complete cycle in response to a non-integer number of global clock cycles, the centralized state machine generating a control signal in response to the counter. The control signal is provided to staging latches, the staging latches generating a clock high signal and a clock low signal, the clock high and clock low signal having patterns derived from a waveform of a target divided ratio clock and the clock high and clock low signals have patterns that match the targeted divided clock frequency and duty cycle. Local pass gate are provided for generating an (n+0.5)-to-1 clock signal in response to the global clock signal, the clock high signal and the clock low signal.Type: GrantFiled: January 27, 2006Date of Patent: April 8, 2008Assignee: International Business Machines CorporationInventors: William V. Huott, Charlie C. Hwang, Timothy G. McNamara
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Patent number: 7146520Abstract: A method and apparatus for operating a clock in a processor having asymmetrically mirrored base-mirror units is disclosed. The method includes initializing a base-unit and a mirror-unit of the processor to the same state, and starting the mirror-unit-clock one clock cycle later than the base-unit-clock.Type: GrantFiled: May 12, 2003Date of Patent: December 5, 2006Assignee: International Business Machines CorporationInventors: Michael Billeci, Timothy G. McNamara, Ching-Lung L. Tong, David Webber