Abstract: A digital system and method of operating the same. The system comprises a processor chip including a first elastic interface domain, wherein the first elastic interface domain comprises a first processor X logic and a first processor Y logic, wherein the first processor X and Y logic comprise first X and Y latches, respectively; and a first ASIC chip electrically coupled to the processor chip, wherein the first processor X and Y logics are configured to be simultaneously in a functional mode, wherein the first processor X logic is configured to switch from the functional mode to a scanning mode while the first processor Y logic remains in the functional mode, and wherein in response to the first processor Y logic being in the functional mode, the first processor Y logic is configured to generate a first reference ASIC clock signal to the first ASIC chip.

Abstract: A method for generating a local clock domain within an operation includes steps of: receiving a clock frequency measurement for a slow portion of logic within the operation; generating a local signal to indicate commencement of the operation and to function as a clock gating signal; latching the clock gating signal to a selected cycle; generating clock domain controls based on the clock gating signal such that the operation times itscommencement on the selected cycle; and propagating the clock gating signal in ungated latches for a number of cycles, such that a second operation is restricted from being launched until the operation completes.

Abstract: A digital system and method of operating the same. The system comprises a processor chip including a first elastic interface domain, wherein the first elastic interface domain comprises a first processor X logic and a first processor Y logic, wherein the first processor X and Y logic comprise first X and Y latches, respectively; and a first ASIC chip electrically coupled to the processor chip, wherein the first processor X and Y logics are configured to be simultaneously in a functional mode, wherein the first processor X logic is configured to switch from the functional mode to a scanning mode while the first processor Y logic remains in the functional mode, and wherein in response to the first processor Y logic being in the functional mode, the first processor Y logic is configured to generate a first reference ASIC clock signal to the first ASIC chip.

Abstract: A method for generating a local clock domain within an operation includes steps of: receiving a clock frequency measurement for a slow portion of logic within the operation; generating a local signal to indicate commencement of the operation and to function as a clock gating signal; latching the clock gating signal to a selected cycle; generating clock domain controls based on the clock gating signal such that the operation times its commencement on the selected cycle; and propagating the clock gating signal in ungated latches for a number of cycles, such that a second operation is restricted from being launched until the operation completes.

Abstract: An X-Y grid tree clock distribution network for distributing a clock signal across a VLSI chip. Tunable wiring tree networks are combined with an X-Y grid vertically and horizontally connecting all the tree end points. No drivers are necessary at connection points of the tree end points to the X-Y grid. The final X-Y grid distributes the clock signal close to every place it is needed, and reduces skew across local regions. A tuning method allows buffering of the clock signal, while minimizing both nominal clock skew and clock uncertainty. The tuned tree networks provide low skew even with variations in clock load density and non-ideal buffer placement, while minimizing the number of buffers needed. The tuning method first represents a total capacitance of one or more of clock pin loads and twig wiring as a clustered grid load. Next, a smoothing of the clustered grid loads approximates the effect of the X-Y grid.

Abstract: An X-Y grid tree clock distribution network for distributing a clock signal across a VLSI chip. Tunable wiring tree networks are combined with an X-Y grid vertically and horizontally connecting all the tree end points. No drivers are necessary at connection points of the tree end points to the X-Y grid. The final X-Y grid distributes the clock signal close to every place it is needed, and reduces skew across local regions. A tuning method allows buffering of the clock signal, while minimizing both nominal clock skew and clock uncertainty. The tuned tree networks provide low skew even with variations in clock load density and non-ideal buffer placement, while minimizing the number of buffers needed. The tuning method first represents a total capacitance of one or more of clock pin loads and twig wiring as a clustered grid load. Next, a smoothing of the clustered grid loads approximates the effect of the X-Y grid.

Abstract: A system for improving system cycle time while supporting 1½ cycle data paths with a PLL based clock system using a communication circuit providing a first mode of operation whereby a first cycle time is obtained, and for allowing use of a second mode of operation whereby a second longer multi-mode cycle time is obtained to extend the time for evaluation of data on the bi-directional data path between a first chip and a memory circuit.

Abstract: A system and method for enabling chips which operate at different frequencies to communicate and which insures synchronous data transfers while maintaing data integrity during clock starting and stopping for multiple chip intercommunication enables chips of different techonologies to be used in the same system and yet maintain synchronous communication between chips operating at the different frequencies. The clock chip will issue a signal to all the chips in the system to start their clocks and begin processing data between two chips that run at different frequency multiples with a fast chip communicating to a chip that is a gear ratio of X times as slow and knowing when to send and receive data at the slow chips rate in order to guarantee that all transfers complete successfully. The slow chip knows when it initiates a launch to the fast chip, the fast chip has had its clocks running long enough to receive that data. A logic mechinism is provided to stop the clocks to all the chips in the system.

Abstract: A reduction of multichip module computer system cycle time is achieved by using a voltage regulator for power supply noise attenuation to reduce jitter. The circuit for doing this includes an active filter network circuit for use in the multichip module of a computer system which generates a quiet analog VDD coupled directly to ground by using the low impedance power supply distributions which already exist in the module. The active filter network permits taking the power supply voltage from the module and stepping it down to a voltage needed by a phased lock loop via an active filter, said active filter comprising an op-amplifier and a source follower and a large value on module capacitor for a resistor network. The capacitor and resistor network acts as a filter with a large time constant where noise appearing on VDD,MOD is completely attenuated by this high value capacitor and resistor network part of our active filter network.

Abstract: A method for dynamic bandwidth testing of a link between two computer subsystems useful for determining the amount of data which can be buffered in a transmission line by delay, in which at each end of the line circuit modules are provided to couple the subsystem by a bi-directional multi-bit (BiDi) link, and providing within each said circuit module a built-in circuit and logic for dynamic transmission characterization and test of a said BiDi link between computer subsystems using built-in characterization logic macros, and during a test mode, switching said said built-in circuit and logic to test mode and using the test mode to characterize the link performance, and after the completion of characterization, the switching built-in characterization logic macros back to a normal system mode after programmatically setting timing parameters for the BiDi link to ensure safe operation of data transfer before the BiDi link is switched to system mode.

Abstract: A chip-to-chip Cycle Alignment Circuit is implemented on the CP chip with a phased lock loop so that a chip knows what is the cycle of a connected chip. Once the PLL is locked, the timing relationship is developed between a reference oscillator and the 3.5 ns on-chip clock which clocks three latches (latch 1,2,3). The Cycle Alignment Circuit has a first part for a rising edge detecting clock chopper and the second part for a self resetting toggle latch. The rising edge detecting clock chopper works by detecting the reference oscillator's rising edge after it has gone through a small delay. The purpose of this delay is to ensure that a latch 1 detects the rising edge on the second 3.5 ns cycle after the reference oscillator rises. A latch 2 is then used to generate a one (3.5 ns) cycle pulse at point that starts on the second 3.5 ns cycle and ends on the third 3.5 ns cycle. The pulse that is produced at that point forces a latch 3 to be reset to a 1 at the beginning of cycle 3.

Abstract: A lock circuit for indicating a locked/unlocked condition of phased lock loops circuits, which uses a reference clock signal input to a good-cycle counter and to a bad-cycle counter to signal a set/reset latch to output a signal indicating whether or not the phase of the output signal and input clock are in phase. Phase detector inputs are XOR gated to produce a pulse when the phase locked output clock is in a bad cycle indicated by the phase locked output clock not being in-phase with its input clock. Pulses on the XOR gate output on a bad cycle feed a single cycle counter reset circuit. The single cycle counter reset circuit on every cycle resets one of the bad and good counters based on its detection of a bad cycle pulse from the XOR gate. The good-cycle counter's output is to the SET input of the set/reset latch, and the bad-cycle counter's output is to the RESET input of the set/reset latch . We enable specific cycling of both the good and bad counters.