Abstract: Methods and systems are provided for a redox flow battery system. In one example, a method of operating a redox flow battery system includes switching the redox flow battery system to an idle mode and completely draining electrolytes from one or more electrode compartments of the redox flow battery system. The one or more electrode compartments may be purged with a gas and refilled with fresh electrolytes.

Abstract: Methods and systems are provided for a rebalancing reactor of a flow battery system. In one example, a pH of a battery electrolyte may be maintained by the rebalancing reactor by applying a negative potential to a catalyst bed of the rebalancing reactor. A performance of the rebalancing reactor may further be maintained by treating the catalyst bed with deionized water.

Abstract: A rebalancing reactor for a redox flow battery system may include a plurality of reactor vessels arranged in stages, each vessel of the plurality of reactor vessels housing a catalyst bed. In one example, the rebalancing reactor is fluidly coupled to an electrolyte storage tank and configured to flow electrolyte through the plurality of reactor vessels, enabling a chemical rebalancing of electrolyte in the redox flow battery cell.

Abstract: Methods and systems are provided for iron preformation in a redox flow battery. In one example, a method may include, in a first condition, discharging and then charging the redox flow battery, and in a second condition, charging the redox flow battery including preforming iron metal at a negative electrode of the redox flow battery, and thereafter entering an idle mode of the redox flow battery including adjusting one or more electrolyte conditions. In some examples, each of preforming the iron metal and adjusting the one or more electrolyte conditions may increase a battery charge capacity to greater than a threshold battery charge capacity.

Abstract: Systems and methods for operating an electric energy storage device are described. The systems and methods may generate a state of charge estimate that is based on negative electrode plating. An overall state of charge may be determined from the state of charge estimate that is based on negative electrode plating and a state of charge estimate that is not based on negative electrode plating.

Abstract: Systems and methods for operating an electric energy storage device are described. The systems and methods may generate a state of charge estimate that is based on negative electrode plating. An overall state of charge may be determined from the state of charge estimate that is based on negative electrode plating and a state of charge estimate that is not based on negative electrode plating.

Abstract: Methods and systems are provided for a rebalancing reactor of a flow battery system. In one example, a pH of a battery electrolyte may be maintained by the rebalancing reactor by applying a negative potential to a catalyst bed of the rebalancing reactor. A performance of the rebalancing reactor may further be maintained by treating the catalyst bed with deionized water.

Abstract: Systems and methods for operating an electric energy storage device are described. The systems and methods may generate a state of charge estimate that is based on negative electrode plating. An overall state of charge may be determined from the state of charge estimate that is based on negative electrode plating and a state of charge estimate that is not based on negative electrode plating.

Abstract: Embodiments of the claimed subject matter are directed to methods and a system that use a standardized grid of clock buffers to automatically route clocks according to a uniform clock grid throughout an ASIC of a non-uniform arrangement of non-uniformly sized logic partitions. According to one embodiment, clock sources and sinks are mapped to grid point locations and a novel grid routing process is performed to link them together. A clock routing macro is assigned to a corresponding partition and associated with the corresponding partition or logic unit according to a partition hierarchy. The underlying routing structure and resources of a clock routing macro are automatically renamed to correspond to the local partition in a script or schedule of programmed instructions, or a routing map. The position of blockages within a partition may also be detected and alternate routes for traversing the blockage may be preemptively determined as well.

Abstract: A method and system for remapping units that are disabled to active units in a 3-D graphics pipeline. Specifically, in one embodiment, a method remaps processing elements in a pipeline of a graphics pipeline unit. Graphical input data are received. Then the number of enabled processing elements are determined from a plurality of processing elements. Each of the enabled processing elements are virtually addressed above a translator to virtually process the graphical input data. Then, the virtual addresses of each of the enabled processing elements are mapped to physical addresses of the enabled processing elements at the translator. The graphical input data are physically processed at the physical addresses of the enabled processing elements. In addition, each of the enabled processing elements are physically addressed below the translator to further process the graphical input data.

Abstract: Embodiments of the claimed subject matter are directed to methods and a system that use a standardized grid of clock buffers to automatically route clocks according to a uniform clock grid throughout an ASIC of a non-uniform arrangement of non-uniformly sized logic partitions. According to one embodiment, clock sources and sinks are mapped to grid point locations and a novel grid routing process is performed to link them together. A clock routing macro is assigned to a corresponding partition and associated with the corresponding partition or logic unit according to a partition hierarchy. The underlying routing structure and resources of a clock routing macro are automatically renamed to correspond to the local partition in a script or schedule of programmed instructions, or a routing map. The position of blockages within a partition may also be detected and alternate routes for traversing the blockage may be preemptively determined as well.

Abstract: A sliding door assembly has a frame with a movable panel and a fixed panel. The movable panel has a pair of rollers that roll along a header located above the panels with the rollers attached to the movable panel via posts that pass through a channel on the header. The posts pass through a curved section of the channel whenever the movable panel is proximate its closed position and a straight section of channel when the movable panel is traveling laterally. The movable panel presses against a gasket located on the frame components surrounding the movable panel wherein one or more latches press the movable panel against the gasket whenever this panel is in the closed position. Valve is positioned within a weep hole on the threshold in order to prevent water from seeping into the building via the bottom of the door assembly.

Abstract: Embodiments of the claimed subject matter are directed to methods and a system that use a standardized grid of clock buffers to automatically route clocks according to a uniform clock grid throughout an ASIC of a non-uniform arrangement of non-uniformly sized logic partitions. According to one embodiment, clock sources and sinks are mapped to grid point locations and a novel grid routing process is performed to link them together. A clock routing macro is assigned to a corresponding partition and associated with the corresponding partition or logic unit according to a partition hierarchy. The underlying routing structure and resources of a clock routing macro are automatically renamed to correspond to the local partition in a script or schedule of programmed instructions, or a routing map. The position of blockages within a partition may also be detected and alternate routes for traversing the blockage may be preemptively determined as well.

Abstract: A sliding door has a sash suspended from a top leg of a frame by having a curved channel extend along this leg and providing the sash with a post that passes through the channel and a roller attached to the post, such that the roller sits on the leg and permits the sash to slide relative to the frame. In closing the door, the sash moves towards the inner portion of the frame and is pressed against a compression gasket that extends about the inner portion of the door in order provide an airtight seal between the sash and the frame. A handle is operatively connected to a dog that is attached to the frame which dog acts on an inner wall of a jamb on the frame in order to maintain the seal.

Abstract: An apparatus for mounting a receiver mast to a structure. The apparatus includes a structure attachment plate, a releasable attachment member, a movable plate releasably attached to the structure attachment plate by the releasable attachment member for movement with respect to the structure attachment plate and a mast fastener for affixing the receiver mast to the movable plate. A leg member may be provided for attaching the structure attachment plate to the structure. A method for mounting a receiver mast to a structure is also disclosed. An assembly mounted to a structure for receiving a signal is also disclosed.

Abstract: A process and implementing computer system for graphics applications in which polygon information, including transparency, color and other polygon characteristics, is organized, stored and transferred in terms of areas or tiled blocks of information in a matrix configuration. The polygon bytes of texel information are organized in an exemplary 8.times.8 matrix row and column format in the graphics subsystem for improved cache-hit efficiency and translated to and from the linear addressing scheme of a host storage device when the host storage is accessed to refill the graphics cache. The bytes comprising the memory tiles of polygon information are arranged such that a complete tile of information is transferred in one burst-mode host memory access to minimize normal multi-line access arbitration and other typical access delays.

Abstract: A graphics controller for use in a computer system stores information from the screen memory portion of its frame buffer in a compressed form, either in a separate compressed data memory or a portion of the frame memory separate from the screen memory. Data in the compressed data memory references color data in a color dictionary. The display controller uses the color data from the compressed data memory to drive the display, thereby reducing accesses to the frame buffer by the display controller. Accordingly, other devices, such as hardware accelerators, have greater opportunities to access the frame buffer.

Abstract: An audio channel system provides an analog signal corresponding to a sound waveform in a computer system. The audio channel system includes a plurality of audio channels. Each audio channel contains a predetermined number of audio data samples for producing a particular sound waveform. A plurality of volume bits define a volume level of each audio data sample to be played. An audio processor processes the sound waveforms of each audio channel. The audio processor acts as a shared processing element which receives the audio data samples from each audio channel. The audio processor divides the audio data samples into a plurality of data such that the plurality of data for each audio data sample is pipelined through the audio processor in a serial manner. The plurality of data for each audio data sample for each audio channel is in various processing stages at any given time.