Abstract: In a transistor in which the majority carriers are holes, at least one narrow bandgap region or layer is doped p-type or contains an excess of holes and is subject to compressive mechanical strain, whereby hole mobility may be significantly increased. In a p-channel quantum well FET, the quantum well InSb well p-type layer 5 (modulation or directly doped) lies between In1-xAlxSb layers 4, 6 where x is of a value sufficient to induce strain in layer 5 to an extent that light and heavy holes are separated by much more than kT. Transistors falling within the invention, including bipolar pnp devices, may be used with their more conventional electron majority carriers counterparts in complementary logic circuitry.

Abstract: The invention provides a Hall effect magnetic field sensor (10, 50) including carrier excluding or extracting means (36, 66) for reducing an intrinsic contribution to carrier concentration in the active region (14e, 53c) to provide for the sensor to be operative in an extrinsic saturated regime. This provides an advantage that magnetic field measurement sensitivity of the sensor (10, 50) can be made substantially insensitive to sensor temperature thereby improving measurement accuracy.

Abstract: An extracting transistor (10)—an FET—includes a conducting channel extending via a p-type InSb quantum well (22) between p-type InAlSb layers (20, 24) of wider band-gap. One of the InAlSb layers (24) incorporates an ultra-thin n-type &dgr;-doping layer (28) of Si, which provides a dominant source of charge carriers for the quantum well (22). It bears n+ source and drain electrodes (30a, 30b) and an insulated gate (30c). The other InAlSb layer (20) adjoins a barrier layer (19) of still wider band-gap upon a substrate layer (14) and substrate (16) with electrode (18). Biasing one or both of the source and drain electrodes (30a, 30b) positive relative to the substrate electrode (18) produces minority carrier extraction in the quantum well (22) reducing its intrinsic contribution to conductivity, taking it into an extrinsic saturated regime and reducing leakage current.

Abstract: A quantum wire field-effect transistor having at least one, one-dimensional, elongate conducting means (14) provided by at least a first semiconductor layer surrounded by a wider bandgap, second semiconductor layer (12, 13) and extending between source (24) and drain (26) electrodes, and in which there is provided a backgate structure (8, 23) to control conduction in the elongate conducting means. The transistor can be a Single Electron Transistor (SET) wherein two adjacent gate electrode (16, 18) are disposed over the elongate conducting means to induce a quantum dot (17) therein, and it can be made with the first semiconductor layer material as GaAs and the second semiconductor layer material as AlGaAs. A method of making the transistor involves preferentially growing the elongate conducting means at the bottom of a groove (6) lined with second semiconductor layer (12).

Abstract: A bipolar transistor having base and collector regions of narrow bandgap semiconductor material and a minority-carrier excluding base contact has a base doping level greater than 1017 cm−3. The transistor has a greater dynamic range, greater AC voltage and power gain-bandwidth products and a lower base access resistance than prior art narrow band-gap bipolar transistors.

Abstract: A bipolar transistor having base and collector regions of narrow bandgap semiconductor material and a minority-carrier excluding base contact has a base doping level greater than 1017 cm−3. The transistor has a greater dynamic range, greater AC voltage and power gain-bandwidth products and a lower base access resistance than prior art narrow band-gap bipolar transistors.

Abstract: A field effect transistor (FET) is of the type which employs base biasing to depress the intrinsic contribution to conduction and reduce leakage current. It incorporates four successive layers (102 to 108): a p+ InSb base layer (102), a p+ InAlSb barrier layer (104), a &pgr; intrinsic layer (106) and an insulating SiO2 layer (108); p+ source and drain regions (110, 112) are implanted in the intrinsic layer (106). The FET is an enhancement mode MISFET (100) in which biasing establishes the FET channel in the intrinsic layer (106). The insulating layer (108) has a substantially flat surface supporting a gate contact (116). This avoids or reduces departures from channel straightness caused by intrusion of a gate groove, and enables a high value of current gain cut-off frequency to be obtained. In FETs with layers that are not flat, departures from channel straightness should not be more than 50 nm in extent, preferably less than 5 nm.

Abstract: The invention provides a Hall effect magnetic field sensor (10, 50) including carrier excluding or extracting means (36, 66) for reducing an intrinsic contribution to carrier concentration in the active region (14e, 53c) to provide for the sensor to be operative in an extrinsic saturated regime. This provides an advantage that magnetic field measurement sensitivity of the sensor (10, 50) can be made substantially insensitive to sensor temperature thereby improving measurement accuracy.

Abstract: An extracting transistor (10)—an FET—includes a conducting channel extending via a p-type InSb quantum well (22) between p-type InAlSb layers (20, 24) of wider band-gap. One of the InAlSb layers (24) incorporates an ultra-thin n-type &dgr;-doping layer (28) of Si, which provides a dominant source of charge carriers for the quantum well (22). It bears n+ source and drain electrodes (30a, 30b) and an insulated gate (30c). The other InAlSb layer (20) adjoins a barrier layer (19) of still wider band-gap upon a substrate layer (14) and substrate (16) with electrode (18). Biasing one or both of the source and drain electrodes (30a, 30b) positive relative to the substrate electrode (18) produces minority carrier extraction in the quantum well (22) reducing its intrinsic contribution to conductivity, taking it into an extrinsic saturated regime and reducing leakage current.

Abstract: A single electron on hole field effect transistor fabricated from a narrow band gap semiconductor. The transistor is such that the valence and conduction bands have sufficiently similar energy levels such that a top region of the valence band at one point (37), e.g. under a gate electrode (34), within the current path of the transistor can be forced to be higher than the bottom region of the conduction band at another point within the transistor, allowing Zener tunelling to occur. The transistor is fabricated from semiconductors with band gaps narrow enough to allow this to occur, for instance InSb and InAISb, CdTe and CDxHg1−xTe.

Abstract: An infra-red detector (10) comprises a detector region (38) and a collector region separated by a barrier region. Operation of these regions is controlled by potentials applied to respective gate electrodes (30, 34, 32), insulated from the detector, barrier and collector regions by an insulating oxide layer (36). The detector, barrier, and collector regions may be arranged on a silicon substrate (24). In operation, photo-excited electrons are generated in the detector region and these cross the barrier region for readout from the collector region.

Abstract: A field effect transistor (FET) is of the type which employs base biasing to depress the intrinsic contribution to conduction and reduce leakage current. It incorporates four successive layers (102 to 108): a p+ InSb base layer (102), a p+ InAlSb barrier layer (104), a &pgr; intrinsic layer (106) and an insulating SiO2 layer (108); p+ source and drain regions (110, 112) are implanted in the intrinsic layer (106). The FET is an enhancement mode MISFET (100) in which biasing establishes the FET channel in the intrinsic layer (106). The insulating layer (108) has a substantially flat surface supporting a gate contact (116). This avoids or reduces departures from channel straightness caused by intrusion of a gate groove, and enables a high value of current gain cut-off frequency to be obtained. In FETs with layers that are not flat, departures from channel straightness should not be more than 50 nm in extent, preferably less than 5 nm.