Abstract: A microcontroller, which addresses program memory separately from data memory, is disclosed. The microcontroller includes a CPU and a boot memory coupled to the CPU. A control is coupled to the CPU and to the boot memory. In a first state, the control causes the boot memory to be configured as data memory. In a second state, the control causes the boot memory to be configured as program memory. A method for loading the boot memory is also disclosed. The method includes configuring the boot memory to be addressed as data memory unless it is already configured to be addressed as data memory, loading a program from an external program memory into the boot memory, configuring the boot memory to be addressed as a program memory, and executing the program in the boot memory. A method for using the microcontroller and method to debug software is described.

Abstract: An improved computer processor architecture in the form of an apparatus with a mirrored stack and method of using the same are provided that enable a processor to recover from an interrupt service routine in one or zero processor instruction cycles. The architecture also removes from software the burden of preserving and maintaining the processor registers upon an interrupt event, thereby improving coding efficiency and the utilization of processor time. The architecture makes it possible to extend faster servicing of interrupts for different levels of interrupt priorities and not just a specific interrupt path. Finally, the architecture provides a mechanism for speeding up CALL and RETURN instruction execution times. In an alternate embodiment, the mirrored stack apparatus is provided with interrupt control logic that has a port to the Program Counter control logic in order to drive directly an interrupt vector address.

Abstract: A current compensating bias generator generates a current which follows voltage. The current compensating bias generator has a bias generator circuit for generating a current. A current compensating circuit is coupled to the bias generator circuit for changing a value of the current as a voltage input to the current compensating bias generator is changed. A resistive ladder circuit is coupled to the current compensating circuit for setting a voltage level trip point for the current compensating circuit at which the current compensating circuit is used to change the value of the current.

Abstract: An improved reprogrammable memory device permits definition of a page within an array of memory cells which is variable in size, erasure of only that data contained within the defined variable page while uneffecting the remaining data in the array of memory cells and reprogramming the defined variable page.

Abstract: A full-swing high voltage data latch for operation at relatively high power supply voltages. The full-swing high voltage data latch has a high voltage rail for supplying an upper voltage level and a low voltage rail for supplying a lower voltage level. A latch circuit is coupled to the upper voltage rail and to the lower voltage rail. The latch circuit is used for generating an output signal. The output signal switches with respect to an input signal when the high voltage rail and the low voltage rail operate in a low voltage mode and is latched in a state that the output signal is currently at when the high voltage rail and the low voltage rail changes state from said low voltage mode to a high voltage mode. An input circuit is coupled to the latch circuit for sending an input signal and a complementary input signal to the latch circuit. An output driver circuit is coupled to the latch circuit for receiving the output signal from the latch circuit and for providing a full-swing output data latch signal.