Abstract: A process of fabricating a memory cell that includes a substrate that has a first region and a second region with a channel therebetween by forming a gate above the channel of the substrate, forming a bitline and siliciding the bitline.

Abstract: A method of programming a memory cell with a substrate that includes a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains a first amount of charge. The method includes applying a lateral electric field within the channel that generates a depletion layer that has electrons at a bottom portion of the depletion layer and applying a vertical electric field within the channel that has a sufficient strength so that the electrons at the bottom portion of the depletion layer are injected into the charge trapping region.

Abstract: A method of programming a memory cell with a substrate that includes a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains a first amount of charge. The method includes applying a constant first voltage across the gate, applying a second constant voltage across the first region and applying a third voltage that is constant and negative to the substrate so that the effect of spillover electrons is substantially reduced when compared with when the third constant voltage is absent.

Abstract: A process for forming an array of memory cells that includes forming a buried bitline region by implanting an n-type dopant in a region of a semiconductor substrate, wherein there is a severe differential change going from the bitline region to the substrate region causing the capacitance of a junction between the bitline region and the semiconductor to be large and reducing the capacitance of the junction.

Abstract: A system and method for providing a memory cell on a semiconductor is disclosed. In one aspect, the method and system include providing at least one gate stack on the semiconductor, depositing at least one spacer, and providing at least one source implant in the semiconductor. The at least one gate stack has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate stack. In another aspect, the method and system include providing at least one gate stack on the semiconductor, providing a first junction implant in the semiconductor, depositing at least one spacer, and providing a second junction implant in the semiconductor after the at least one spacer is deposited. The at least one gate stack has an edge. A portion of the at least one spacer is disposed at the edge of the at least one gate stack.

Abstract: A system and method for providing a memory cell on a semiconductor is disclosed. The method and system include providing an oxide layer on the semiconductor and providing at least one gate stack disposed above the oxide layer. The at least one gate stack has a corner contacting the oxide layer. The method and system further include exposing at least the corner of the at least one gate stack and rounding at least the corner of the at least one gate stack.

Abstract: A method of selectively erasing an individual memory cell of an array of non-volatile memory cells by providing an array of non-volatile memory cells that includes a first non-volatile memory cell that is connected in series with a second non-volatile memory cell and erasing the first non-volatile memory cell while not erasing the second non-volatile memory cell.

Abstract: A method of selectively erasing a bit of an individual memory cell of an array of non-volatile memory cells by providing an array of non-volatile memory cells that include a first non-volatile two bit memory cell that is connected in series with a second non-volatile memory cell. The method includes erasing a first bit of the first non-volatile two bit memory cell while not erasing a second bit of the first non-volatile memory cell.

Abstract: A system and method for controlling a characteristic of at least one memory cell on a semiconductor is disclosed. The at least one memory cell includes a gate stack, a source, and a drain. The semiconductor includes a surface. In one aspect, the method and system include providing the gate stack on the semiconductor and providing the source including a source dopant having a local peak in concentration. The local peak in concentration of the source dopant is located under the gate stack and in proximity to a portion of the surface of the semiconductor. In another aspect the method and system includes a memory cell on a semiconductor. The semiconductor includes a surface. The memory cell includes a gate stack on the semiconductor, a source, and a drain. The gate stack has a first edge and a second edge. The source is located in proximity to the first edge of the gate stack. The drain is located in proximity to the second edge of the gate stack. A first portion of the source is disposed under the gate stack.

Abstract: A method and system for providing a flash memory cell on a semiconductor is disclosed. In one aspect, the method and system include providing a plurality of gate stacks and providing a drain implant at an angle. The plurality of gate stacks define a plurality of drain areas and a plurality of source areas. The angle is measured from a direction perpendicular to the surface of the semiconductor. The angle allows the plurality of gate stacks to block the drain implant from reaching the plurality of source areas. In another aspect, the method and system include providing a plurality of gate stacks and providing a source implant at an angle. The plurality of gate stacks define a plurality of drain areas and a plurality of source areas. The angle is measured from a direction perpendicular to the surface of the semiconductor. The angle allows the plurality of gate stacks to block the source implant from reaching the plurality of drain areas.

Abstract: The present invention provides a method and system for the formation of semiconductor devices which reduces band-to-band tunneling current and short-channel effects. The method and system includes implanting first low-dose arsenic into an area in the substrate, thermally diffusing the first low-dose arsenic through a portion of the substrate, implanting a second higher-dose arsenic into the area in the substrate, and diffusing the second higher-dose arsenic into the area in the substrate. Under the present invention, the combination of the first and second arsenic implants has a graded lateral profile which reduces band-to-band tunneling current and short-channel effects. The method also improves the reliability and performance of the semiconductor devices.

Abstract: A system and method for providing a memory cell on a semiconductor is disclosed. The memory cell has a source and a drain. The method and system include providing a source implant in the semiconductor, providing a pocket implant in the semiconductor, and providing a drain implant in the semiconductor after the pocket implant is provided. Thus, short channel effects are reduced.

Abstract: A system and method for providing a memory cell on a semiconductor is disclosed. In one aspect, the method and system include providing at least one gate stack on the semiconductor, depositing at least one spacer, and providing at least one source implant in the semiconductor. The at least one gate stack has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate stack. In another aspect, the method and system include providing at least one gate stack on the semiconductor, providing a first junction implant in the semiconductor, depositing at least one spacer, and providing a second junction implant in the semiconductor after the at least one spacer is deposited. The at least one gate stack has an edge. A portion of the at least one spacer is disposed at the edge of the at least one gate stack.