Abstract: Methods of forming edge etch protection using dual layers of positive-negative tone resists. According to a method, a wafer substrate is provided. A first type resist is deposited on a surface of the wafer substrate. The first type resist is patterned and a resist ring is created around a peripheral edge of the wafer substrate. The resist ring is cured. A second type resist is deposited on the surface of the wafer substrate and the resist ring. The second type resist is different from the first type resist.

Abstract: Methods of forming edge etch protection using dual layers of positive-negative tone resists. According to a method, a wafer substrate is provided. A first type resist is deposited on a surface of the wafer substrate. The first type resist is patterned and a resist ring is created around a peripheral edge of the wafer substrate. The resist ring is cured. A second type resist is deposited on the surface of the wafer substrate and the resist ring. The second type resist is different from the first type resist.

Abstract: A method and apparatus includes an integrated circuit device, and at least one alignment mark on the integrated circuit device, the alignment mark comprises a first coded region, a second coded region adjacent the first coded region, and a third coded region adjacent the second coded region, the second coded region located between the first coded region and the third coded region, and markings on the first coded region and the third coded region being identical.

Abstract: A method and apparatus includes an integrated circuit device, and at least one alignment mark on the integrated circuit device, the alignment mark comprises a first coded region, a second coded region adjacent the first coded region, and a third coded region adjacent the second coded region, the second coded region located between the first coded region and the third coded region, and markings on the first coded region and the third coded region being identical.

Abstract: A method of forming openings on a semiconductor wafer comprising an initial step of providing a first film layer over the semiconductor wafer. A first opening in the first film layer is created by transferring an image of the first opening from a photoresist layer into the first film layer using an etching procedure. The first opening includes horizontal and vertical surfaces and has first width and height dimensions. After removing the photoresist layer, a second film layer is deposited over the first film layer and the opening such that the opening has a second width and height dimension which is less than the first width and height dimension. The second film layer is then anisotropically etched from the horizontal surface of the first film layer, and the horizontal surface of the opening such that the opening includes the first height dimension and the second width dimension.

Abstract: A method of forming openings on a semiconductor wafer comprising an initial step of providing a first film layer over the semiconductor wafer. A first opening in the first film layer is created by transferring an image of the first opening from a photoresist layer into the first film layer using an etching procedure. The first opening includes horizontal and vertical surfaces and has first width and height dimensions. After removing the photoresist layer, a second film layer is deposited over the first film layer and the opening such that the opening has a second width and height dimension which is less than the first width and height dimension. The second film layer is then anisotropically etched from the horizontal surface of the first film layer, and the horizontal surface of the opening such that the opening includes the first height dimension and the second width dimension.

Abstract: The present invention relates generally to the field of semiconductor device manufacturing, and more specifically to a method for aligning a projected photolithography mask pattern image with respect to the underlying device layer. The method involves measuring the overlay error between product features in the projected layer and product features in the underlying layer, determining an adjustment factor based on these measurements, and applying this adjustment factor to the overlay error between reference features located in the kerf of the projected layer and reference features in the kerf of the underlying layer. Thus, nonzero offsets or adjustment factors for box-in-box overlay targets are entered into a stepper or scanner tool, in order to minimize within field product overlay errors.

Abstract: A method for overlay metrology and control. Simultaneous use of between-field overlay metrology to control field term alignment error at all levels and level-to-level metrology to control field term, grid term, and translation alignment errors at all levels is applied.