Abstract: The present disclosure describes an ultraviolet (UV) sensor configured to detect a target UV spectrum (e.g., UVB spectrum). The UV sensor includes a first photodiode with a first UV spectral response and a second photodiode with a second UV spectral response. A filter layer having a graded spectral response is formed over the second photodiode, and the second UV spectral response is affected by a controlled parameter (e.g., thickness) of the filter layer. The UV sensor further includes a subtraction circuit coupled with the first photodiode and the second photodiode. The subtraction circuit is configured to provide a differential response based on a difference between the first UV spectral response and the second UV spectral response. The controlled parameter of the filter layer can be selected such that the differential response provides a detected spectral response of the target spectrum.

Abstract: Semiconductor devices, such as laterally diffused metal oxide semiconductor (LDMOS) devices, are described that have a field plate connected to a gate of the device. In one or more implementations, the semiconductor devices include a substrate having a source region of a first conductivity type and a drain region of the first conductivity type. A gate is positioned over the surface and between the source region and the drain region. The gate is configured to receive a voltage so that a conduction region may be formed at least partially below the gate to allow majority carriers to travel between the source region and the drain region. The device also includes a field plate at least partially positioned over and connected to the gate. The field plate is configured to shape an electrical field generated between the source region and the drain region when a voltage is applied to the gate.

Abstract: The present disclosure describes an ultraviolet (UV) sensor configured to detect a target UV spectrum (e.g., UVB spectrum). The UV sensor includes a first photodiode with a first UV spectral response and a second photodiode with a second UV spectral response. A filter layer having a graded spectral response is formed over the second photodiode, and the second UV spectral response is affected by a controlled parameter (e.g., thickness) of the filter layer. The UV sensor further includes a subtraction circuit coupled with the first photodiode and the second photodiode. The subtraction circuit is configured to provide a differential response based on a difference between the first UV spectral response and the second UV spectral response. The controlled parameter of the filter layer can be selected such that the differential response provides a detected spectral response of the target spectrum.

Abstract: Semiconductor devices, such as LDMOS devices, are described that include a plurality of trench regions formed in an extended drain region of the devices. In one or more implementations, the semiconductor devices include a substrate having an extended drain region, a source region, and a drain region, all of the first conductivity type, formed proximate to a surface of the substrate. A gate is positioned over the surface and between the source region and the drain region. The gate is configured to receive a voltage so that a conduction region may be formed at least partially below the gate to allow charge carriers (e.g., majority carriers) to travel between the source region and the drain region. A plurality of trench regions are formed within the extended drain region that are configured to increase resistivity within the extended drain region when charge carriers travel between the source region and the drain region.

Abstract: Semiconductor devices are described that include a dual-gate configuration. In one or more implementations, the semiconductor devices include a substrate having a first surface and a second surface. The substrate includes a first and a second body region formed proximal to the first surface. Moreover, each body region includes a source region formed therein. The substrate further includes a drain region formed proximal to the second surface and an epitaxial region that is configured to function as a drift region between the drain region and the source regions. A dual-gate is formed over the first surface of the substrate. The dual-gate includes a first gate region and a second gate region that define a gap there between to reduce the gate to drain capacitance.

Abstract: Semiconductor devices, such as LDMOS devices, are described that include a plurality of trench regions formed in an extended drain region of the devices. In one or more implementations, the semiconductor devices include a substrate having an extended drain region, a source region, and a drain region, all of the first conductivity type, formed proximate to a surface of the substrate. A gate is positioned over the surface and between the source region and the drain region. The gate is configured to receive a voltage so that a conduction region may be formed at least partially below the gate to allow charge carriers (e.g., majority carriers) to travel between the source region and the drain region. A plurality of trench regions are formed within the extended drain region that are configured to increase resistivity within the extended drain region when charge carriers travel between the source region and the drain region.

Abstract: Semiconductor devices are described that include a dual-gate configuration. In one or more implementations, the semiconductor devices include a substrate having a first surface and a second surface. The substrate includes a first and a second body region formed proximal to the first surface. Moreover, each body region includes a source region formed therein. The substrate further includes a drain region formed proximal to the second surface and an epitaxial region that is configured to function as a drift region between the drain region and the source regions. A dual-gate is formed over the first surface of the substrate. The dual-gate includes a first gate region and a second gate region that define a gap there between to reduce the gate to drain capacitance.