Abstract: Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.

Abstract: Embodiments of the present invention generate equations that model a synchronous circuit that contains sequential elements, which may include transparent elements, and a plurality of multiple-phase clocks. Phase-related information is assigned to nodes of the circuit. The phase-related information describes input and output characteristics at nodes of the circuit as the characteristics relate to clock phases. Equations are formed that model signals at the circuit nodes based on the phase-related information.

Abstract: Embodiments of the present invention generate equations that model a synchronous circuit that contains sequential elements, which may include transparent elements, and a plurality of multiple-phase clocks. Phase-related information is assigned to nodes of the circuit. The phase-related information describes input and output characteristics at nodes of the circuit as the characteristics relate to clock phases. Equations are formed that model signals at the circuit nodes based on the phase-related information.