Abstract: A programmable logic core (PLC) can be integrated into custom ICs such as ASICs and SOCs using a unique design methodology. For example, the methodology can incorporate the PLC into the entire ASIC design process from chip level RTL to final tape-out and resolve issues ranging from RTL guidelines through to sub-micron signal integrity. The post-manufacture programming flow is considered up-front during the ASIC flow and tools ensure successful programming in the field environment for the lifetime of the product. An example PLC architecture for integration into a custom IC includes a Multi Scale Array (MSA) that consists of an array of configurable ALUs and is implemented as a hard macro, an Application Circuit Interface (ACI) that provides signal interface between the MSA and application circuitry and is included in the same hard macro, and a PLC Adapter that initiates and loads the PLC configuration data and interfaces that is implemented as a soft-macro.

Abstract: A high capacity gate array which incorporates an effectively three dimensional interconnect network. The array is formed from multiple smaller arrays which are connected to a common substrate by means of flip-chip bonding. The substrate is typically a multi-layer substrate which has interconnect lines embedded on or within it, thereby allowing a set of desired interconnections between the smaller logic cell arrays to be implemented. The contact points for connecting logic cells or arrays of cells to the substrate result from placing a multitude of solder bumps on the smaller arrays of logic cells at desired interconnect points. Connecting the interconnect point solder bumps to the multi-layer substrate then permits the individual logic cell arrays to be interconnected in a desired manner. A three dimensional interconnect network is realized by interconnecting corresponding points on different logic cell arrays so that the arrays are connected in parallel.

Abstract: In an FDDI token ring network, a repeat filter that treats FDDI Set and Reset symbols occurring in a frame prior to an End Delimiter symbol as a violation and does not repeat these symbols onto the FDDI ring. In addition to the three states described in the FDDI repeat filter standard for a byte-wide implementation, a repeat filter in accordance with the present invention includes a fourth END state. The presence of this END state allows the REPEAT state to be restricted such that it treats bytes within a frame with either symbol of the byte being either a Set or Reset symbol as a violation and a Halt byte is transmitted onto the ring; the repeat filter then enters the Halt state. In addition, the repeat filter is also responsive to "mixed" bytes that consist of an FDDI data symbol and an FDDI control symbol.

Abstract: Preamble smoothing for information character transmissions in a data transmission network is accomplished as follows. First, the smoothing filter identifies the start of a new preamble. If the start of a new preamble is identified and a previously received preamble has been extended, then the preamble is contacted by deleting an IDLE byte or, if the frame received prior to the initial IDLE byte was a frame fragment, then the information character preceding the initial IDLE byte is deleted. Following the contraction of the preamble, a determination is made as to whether next received byte is an IDLE byte. If it is not, then the preamble is extended by inserting an IDLE byte and the smoothing filter begins searching for the start of a new preamble. If it is, then a counter is incremented. If the counter has not yet reached its preset threshold, then the next byte is checked to determine whether it is an IDLE byte. If it is, then the counter is again incremented.

Abstract: According to the present invention, each successive refresh to the multiple banks of a DRAM array is staggered by one clock period. Thus, the time required to refresh one row in each DRAM of each bank at 10 MHz, for example, is equal to 0.7 .mu.sec., or 4.4% of the total allowable maximum time between refresh cycles. This staggered refresh technique avoids large power supply current spikes while minimizing the effect on memory access bandwidth.

Abstract: A three state inverter driver is operated so that its output goes to a logic one briefly just prior to going to its high impedance state when commanded by a disable pulse. This characteristic is useful where a plurality of drivers are employed to operate a DRAM element.