Patents by Inventor Timothy Lawrence Canepa

Timothy Lawrence Canepa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10061727
    Abstract: A paired queue apparatus and method comprising request and response queues wherein queue head and tail pointer update values are communicated through an enhanced pointer word data format providing pointer indicator information and optional auxiliary information in a single transfer, wherein auxiliary information provides additional system communication without consuming additional bandwidth. Auxiliary information is optionally contained in a response data entry written to a response queue or in a request entry written to a request queue.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: August 28, 2018
    Assignee: Seagate Technology LLC
    Inventors: Timothy Lawrence Canepa, Earl T. Cohen
  • Patent number: 10025735
    Abstract: A decoupled Direct Memory Access (DMA) architecture includes at least two DMA controllers, and optionally at least one of the DMA controllers is operable to assert a lock signal operable to selectively inhibit write access to at least a portion of one system data storage element. The DMA controllers are optionally operable to communicate pending task information and to reschedule pending tasks of at least one the DMA controllers. Optionally data is transferred from at least a first one of the DMA controllers to one or more function units, and processed data from the function units is provided to at least a second one of the DMA controllers. Optionally the DMA controllers and one or more memory elements accessible to the DMA controllers are implemented as part of an I/O device.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: July 17, 2018
    Assignee: Seagate Technology LLC
    Inventors: Earl T Cohen, Timothy Lawrence Canepa
  • Publication number: 20170052912
    Abstract: A paired queue apparatus and method comprising request and response queues wherein queue head and tail pointer update values are communicated through an enhanced pointer word data format providing pointer indicator information and optional auxiliary information in a single transfer, wherein auxiliary information provides additional system communication without consuming additional bandwidth. Auxiliary information is optionally contained in a response data entry written to a response queue or in a request entry written to a request queue.
    Type: Application
    Filed: August 24, 2016
    Publication date: February 23, 2017
    Applicant: Seagate Technology LLC
    Inventors: Timothy Lawrence CANEPA, Earl T. COHEN
  • Patent number: 9436634
    Abstract: A paired queue apparatus and method comprising request and response queues wherein queue head and tail pointer update values are communicated through an enhanced pointer word data format providing pointer indicator information and optional auxiliary information in a single transfer, wherein auxiliary information provides additional system communication without consuming additional bandwidth. Auxiliary information is optionally contained in a response data entry written to a response queue or in a request entry written to a request queue.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: September 6, 2016
    Assignee: Seagate Technology LLC
    Inventors: Timothy Lawrence Canepa, Earl T. Cohen
  • Patent number: 9423977
    Abstract: Lock-free communication storage request reordering enables reduced latency and/or increased bandwidth in some usage scenarios, such as a multi-threaded driver context operating with a device, such as a storage device (e.g. a Solid-State Disk (SSD)) enabled to respond to a multiplicity of outstanding requests.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: August 23, 2016
    Assignee: Seagate Technology LLC
    Inventor: Timothy Lawrence Canepa
  • Patent number: 9395924
    Abstract: Management of and region selection for writes to non-volatile memory of an SSD improves performance, reliability, unit cost, and/or development cost of an SSD. A controller receives and determines characteristics of writes (e.g. by analyzing the write data, the write data source, and/or by receiving a hint) and selects a region based on the determined characteristics and properties of regions of non-volatile memory. For example, a controller receives writes determined to be read-only data and selects regions of non-volatile memory containing cells that are likely to have write failures. By placing read-only data in write failure prone regions, the likelihood of an error is reduced, thus improving reliability. As another example, a controller receives writes hinted to be uncompressible and selects regions of non-volatile memory containing uncompressible data.
    Type: Grant
    Filed: January 19, 2014
    Date of Patent: July 19, 2016
    Assignee: Seagate Technology LLC
    Inventors: Earl T Cohen, Timothy Lawrence Canepa
  • Patent number: 9189385
    Abstract: Scalable control/management data structures enable optimizing performance and/or attempting to achieve a particular performance target of an SSD in accordance with host interfacing, number of NVM devices, NVM characteristics and size, and NVM aging and performance decline. Pre-scaled data structures are included in SSD controller firmware loadable at system initialization. Static data structure configurations enable load-once-operate-for-product-lifetime operation for consumer applications. Dynamic configurations provide sequences of data structures pre-scaled to optimize operation as NVM ages and performance declines. Pre-configured adjustments in data structure size included in consecutive configurations periodically replace earlier configurations at least one time during product lifetime, producing a periodic rescaling of data structure size to track changes in aging NVM.
    Type: Grant
    Filed: October 15, 2012
    Date of Patent: November 17, 2015
    Assignee: Seagate Technology LLC
    Inventors: Earl T. Cohen, Timothy Lawrence Canepa
  • Patent number: 9183140
    Abstract: Higher-level redundancy information computation enables a Solid-State Disk (SSD) controller to provide higher-level redundancy capabilities to maintain reliable operation in a context of failures of non-volatile (e.g. flash) memory elements during operation of an SSD. A first portion of higher-level redundancy information is computed using parity coding via an XOR of all pages in a portion of data to be protected by the higher-level redundancy information. A second portion of the higher-level redundancy information is computed using a weighted-sum technique, each page in the portion being assigned a unique non-zero “index” as a weight when computing the weighted-sum. Arithmetic is performed over a finite field (such as a Galois Field). The portions of the higher-level redundancy information are computable in any order, such as an order based on order of read operation completion of non-volatile memory elements.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: November 10, 2015
    Assignee: Seagate Technology LLC
    Inventors: Jeremy Isaac Nathaniel Werner, Leonid Baryudin, Timothy Lawrence Canepa, Earl T. Cohen
  • Patent number: 9116624
    Abstract: Techniques using scalable storage devices represent a plurality of host-accessible storage devices as a single logical interface, conceptually aggregating storage implemented by the devices. A primary agent of the devices accepts storage requests from the host using a host-interface protocol, processing the requests internally and/or forwarding the requests as sub-requests to secondary agents of the storage devices using a peer-to-peer protocol. The secondary agents accept and process the sub-requests, and report sub-status information for each of the sub-requests to the primary agent and/or the host. The primary agent optionally accumulates the sub-statuses into an overall status for providing to the host. Peer-to-peer communication between the agents is optionally used to communicate redundancy information during host accesses and/or failure recoveries. Various failure recovery techniques reallocate storage, reassign agents, recover data via redundancy information, or any combination thereof.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: August 25, 2015
    Assignee: Seagate Technology LLC
    Inventors: Timothy Lawrence Canepa, Carlton Gene Amdahl
  • Patent number: 9105305
    Abstract: A Solid-State Disk (SSD) controller enables dynamic higher-level redundancy mode management with independent silicon elements to provide graceful degradation as non-volatile (e.g. flash) memory elements fail during operation of an SSD implemented by the controller. Higher-level error correction provides correction of lower-level uncorrectable errors. If a failure of one of the non-volatile memory elements is detected, then the higher-level error correction is dynamically transitioned from operating in a current mode to operating in a new mode. The transition includes one or more of reducing free space available on the SSD, rearranging data storage of the SSD, recovering/storing failed user data (if possible), and determining/storing revised higher-level error correction information. Operation then continues in the new mode. If another failure of the non-volatile memory elements is detected, then another transition is made to another new mode.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: August 11, 2015
    Assignee: Seagate Technology LLC
    Inventors: Jeremy Isaac Nathaniel Werner, Leonid Baryudin, Timothy Lawrence Canepa, Earl T Cohen
  • Publication number: 20140281083
    Abstract: A paired queue apparatus and method comprising request and response queues wherein queue head and tail pointer update values are communicated through an enhanced pointer word data format providing pointer indicator information and optional auxiliary information in a single transfer, wherein auxiliary information provides additional system communication without consuming additional bandwidth. Auxiliary information is optionally contained in a response data entry written to a response queue or in a request entry written to a request queue.
    Type: Application
    Filed: March 13, 2014
    Publication date: September 18, 2014
    Applicant: LSI CORPORATION
    Inventors: Timothy Lawrence CANEPA, Earl T. COHEN
  • Publication number: 20140281171
    Abstract: Lock-free communication storage request reordering enables reduced latency and/or increased bandwidth in some usage scenarios, such as a multi-threaded driver context operating with a device, such as a storage device (e.g. a Solid-State Disk (SSD)) enabled to respond to a multiplicity of outstanding requests.
    Type: Application
    Filed: March 6, 2014
    Publication date: September 18, 2014
    Applicant: LSI CORPORATION
    Inventor: Timothy Lawrence CANEPA
  • Publication number: 20140258598
    Abstract: Techniques using scalable storage devices represent a plurality of host-accessible storage devices as a single logical interface, conceptually aggregating storage implemented by the devices. A primary agent of the devices accepts storage requests from the host using a host-interface protocol, processing the requests internally and/or forwarding the requests as sub-requests to secondary agents of the storage devices using a peer-to-peer protocol. The secondary agents accept and process the sub-requests, and report sub-status information for each of the sub-requests to the primary agent and/or the host. The primary agent optionally accumulates the sub-statuses into an overall status for providing to the host. Peer-to-peer communication between the agents is optionally used to communicate redundancy information during host accesses and/or failure recoveries. Various failure recovery techniques reallocate storage, reassign agents, recover data via redundancy information, or any combination thereof.
    Type: Application
    Filed: March 4, 2014
    Publication date: September 11, 2014
    Applicant: LSI CORPORATION
    Inventors: Timothy Lawrence CANEPA, Carlton Gene AMDAHL
  • Publication number: 20140237166
    Abstract: Higher-level redundancy information computation enables a Solid-State Disk (SSD) controller to provide higher-level redundancy capabilities to maintain reliable operation in a context of failures of non-volatile (e.g. flash) memory elements during operation of an SSD. A first portion of higher-level redundancy information is computed using parity coding via an XOR of all pages in a portion of data to be protected by the higher-level redundancy information. A second portion of the higher-level redundancy information is computed using a weighted-sum technique, each page in the portion being assigned a unique non-zero “index” as a weight when computing the weighted-sum. Arithmetic is performed over a finite field (such as a Galois Field). The portions of the higher-level redundancy information are computable in any order, such as an order based on order of read operation completion of non-volatile memory elements.
    Type: Application
    Filed: February 14, 2014
    Publication date: August 21, 2014
    Applicant: LSI Corporation
    Inventors: Jeremy Isaac Nathaniel WERNER, Leonid BARYUDIN, Timothy Lawrence CANEPA, Earl T. COHEN
  • Publication number: 20140215103
    Abstract: A decoupled Direct Memory Access (DMA) architecture includes at least two DMA controllers, and optionally at least one of the DMA controllers is operable to assert a lock signal operable to selectively inhibit write access to at least a portion of one system data storage element. The DMA controllers are optionally operable to communicate pending task information and to reschedule pending tasks of at least one the DMA controllers. Optionally data is transferred from at least a first one of the DMA controllers to one or more function units, and processed data from the function units is provided to at least a second one of the DMA controllers. Optionally the DMA controllers and one or more memory elements accessible to the DMA controllers are implemented as part of an I/O device.
    Type: Application
    Filed: January 22, 2014
    Publication date: July 31, 2014
    Inventors: Earl T. COHEN, Timothy Lawrence CANEPA
  • Publication number: 20140208007
    Abstract: Management of and region selection for writes to non-volatile memory of an SSD improves performance, reliability, unit cost, and/or development cost of an SSD. A controller receives and determines characteristics of writes (e.g. by analyzing the write data, the write data source, and/or by receiving a hint) and selects a region based on the determined characteristics and properties of regions of non-volatile memory. For example, a controller receives writes determined to be read-only data and selects regions of non-volatile memory containing cells that are likely to have write failures. By placing read-only data in write failure prone regions, the likelihood of an error is reduced, thus improving reliability. As another example, a controller receives writes hinted to be uncompressible and selects regions of non-volatile memory containing uncompressible data.
    Type: Application
    Filed: January 19, 2014
    Publication date: July 24, 2014
    Applicant: LSI CORPORATION
    Inventors: Earl T. COHEN, Timothy Lawrence CANEPA
  • Publication number: 20140108703
    Abstract: Scalable control/management data structures enable optimizing performance and/or attempting to achieve a particular performance target of an SSD in accordance with host interfacing, number of NVM devices, NVM characteristics and size, and NVM aging and performance decline. Pre-scaled data structures are included in SSD controller firmware loadable at system initialization. Static data structure configurations enable load-once-operate-for-product-lifetime operation for consumer applications. Dynamic configurations provide sequences of data structures pre-scaled to optimize operation as NVM ages and performance declines. Pre-configured adjustments in data structure size included in consecutive configurations periodically replace earlier configurations at least one time during product lifetime, producing a periodic rescaling of data structure size to track changes in aging NVM.
    Type: Application
    Filed: October 15, 2012
    Publication date: April 17, 2014
    Applicant: LSI CORPORATION
    Inventors: Earl T. COHEN, Timothy Lawrence CANEPA
  • Patent number: 8677068
    Abstract: Techniques using scalable storage devices represent a plurality of host-accessible storage devices as a single logical interface, conceptually aggregating storage implemented by the devices. A primary agent of the devices accepts storage requests from the host using a host-interface protocol, processing the requests internally and/or forwarding the requests as sub-requests to secondary agents of the storage devices using a peer-to-peer protocol. The secondary agents accept and process the sub-requests, and report sub-status information for each of the sub-requests to the primary agent and/or the host. The primary agent optionally accumulates the sub-statuses into an overall status for providing to the host. Peer-to-peer communication between the agents is optionally used to communicate redundancy information during host accesses and/or failure recoveries. Various failure recovery techniques reallocate storage, reassign agents, recover data via redundancy information, or any combination thereof.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: March 18, 2014
    Assignee: LSI Corporation
    Inventors: Timothy Lawrence Canepa, Carlton Gene Amdahl
  • Publication number: 20130297894
    Abstract: An I/O device is coupled to a computing host. In some embodiments, the device is enabled to utilize memory of the computing host not directly coupled to the device to store information such as a shadow copy of a map of the device and/or state of the device. Storage of the shadow copy of the map enables one or both of the device and the computing host to utilize the shadow copy of the map, such as to decrease read latency. Storage of the state enables the device to save volatile state that would otherwise be lost when the device enters a low-power state. In some embodiments, the device implements one or more non-standard modifiers of standard commands. The non-standard modifiers modify the execution of the standard commands, providing features not present in a host protocol having only the standard commands.
    Type: Application
    Filed: July 5, 2013
    Publication date: November 7, 2013
    Inventors: Earl T. COHEN, Timothy Lawrence CANEPA
  • Publication number: 20130246839
    Abstract: A Solid-State Disk (SSD) controller enables dynamic higher-level redundancy mode management with independent silicon elements to provide graceful degradation as non-volatile (e.g. flash) memory elements fail during operation of an SSD implemented by the controller. Higher-level error correction provides correction of lower-level uncorrectable errors. If a failure of one of the non-volatile memory elements is detected, then the higher-level error correction is dynamically transitioned from operating in a current mode to operating in a new mode. The transition includes one or more of reducing free space available on the SSD, rearranging data storage of the SSD, recovering/storing failed user data (if possible), and determining/storing revised higher-level error correction information. Operation then continues in the new mode. If another failure of the non-volatile memory elements is detected, then another transition is made to another new mode.
    Type: Application
    Filed: November 30, 2011
    Publication date: September 19, 2013
    Applicant: LSI CORPORATION
    Inventors: Jeremy Isaac Nathaniel Werner, Leonid Baryudin, Timothy Lawrence Canepa, Earl T. Cohen