Abstract: A test pattern generator for a semiconductor integrated circuit tester comprises a DRAM for receiving and storing test pattern data in blocks and a SRAM for storing checking data in units, wherein each unit of checking data stored in the SRAM bears a predetermined relationship to a corresponding block received by the DRAM. A DRAM sequencer addresses the DRAM for reading the blocks of test pattern data in a predetermined order and a SRAM sequencer addresses the SRAM for reading the units of checking data from the SRAM. A validating circuit receives a block of test pattern data read from the DRAM and the corresponding unit of checking data read from the SRAM and provides an output which indicates whether the unit of checking data is in the predetermined relationship with the block.

Abstract: A system for stabilizing a delay through a signal path of an integrated circuit (IC) includes an oscillator for producing a periodic first reference signal, a delay circuit for delaying the first reference signal to produce a periodic second reference signal, and a loop controller for adjusting the magnitude of the IC's power supply so as to maintain a constant phase difference between the first and second reference signals. By adjusting the power supply magnitude, the loop controller also stabilizes signal path delays through logic circuits implemented in the IC. The oscillator is formed by a logic gate implemented in the IC and a passive delay line feeding the logic gate's output back to its input. The delay of the delay circuit is programmably adjustable to allow for adjustment of the signal path delay through the IC.

Abstract: A system for compensating for thermal drift of an output signal (OUT1) produced by a logic circuit in response to an input CLOCK signal after a temperature dependent delay includes a variable delay circuit, an oscillator and a digital phase lock controller. The delay circuit delays the OUT1signal to produce a compensated output signal (OUT2) with a variable delay controlled by input CONTROL data. The oscillator generates an output signal (OSC.sub.-- OUT) having a period also controlled by the input CONTROL data which is substantially proportional to the sum of the temperature dependent delay of the logic circuit and the delay of the variable delay circuit. The digital phase lock controller continually monitors the period of the OSC.sub.-- OUT signal and adjusts the CONTROL data so that the period of the OSC.sub.-- OUT signal remains substantially constant. This ensures that the delay between the CLOCK signal and OUT2 remains constant despite temperature dependent variations in the delay of the logic circuit.