Abstract: A decorative, nonwoven laminate and a method of forming, including a first side of a first nonwoven affixed to one or both of a) a first side of a polymeric sheet or b) a second nonwoven, wherein the first nonwoven exhibits a basis weight of 15 g/m2 to 2500 g/m2 and the second nonwoven exhibits a basis weight of 15 g/m2 to 1200 g/m2; and a colorant deposited on a second side of the first nonwoven. A topical coating may or may not be applied to improve durability of the printed surface layer. The decorative nonwoven laminate may also amount to a single layer of the first nonwoven, which then includes a layer of colorant and a topical coating over the colorant and single nonwoven layer.

Abstract: A method of installing a stator and a motor housing includes inserting a stator into a motor housing, the motor housing having a shaft bore and a plurality first bolt holes end of the state are having a bore opening and a plurality of second bolt holes. A centering fixture is inserted into the shaft bore of the housing and into the bore opening, the centering fixture includes a first centering device received into the shaft bore and a second centering device received into the bore opening of the stator. A locating plate is secured to the motor housing and engaged with the centering fixture. The first centering devices actuated for centering the centering fixture relative to the shaft and the second centering device is actuated for centering the state are relative to the shaft board. The plurality of bolts are tightened to secure the stator to the motor housing.

Abstract: A method for gel curing a varnish of a stator assembly includes: applying an electrically-insulating material to a plurality of electrical conductors of a stator assembly; monitoring a temperature of the stator assembly using at least one temperature sensor; determining whether the temperature of the stator assembly has reached a target temperature; in response to determining that the temperature of the stator assembly is equal to the target temperature, heating the stator assembly using an induction heating element to maintain the temperature of the stator assembly at the target temperature for a predetermined amount of time; determining whether the temperature of the stator assembly is equal to the final target temperature; in response to determining that the target temperature is not equal to the final target temperature, increasing the target temperature by a predetermined amount of degrees.

Abstract: A method for gel curing a varnish of a stator assembly includes: applying an electrically-insulating material to a plurality of electrical conductors of a stator assembly; monitoring a temperature of the stator assembly using at least one temperature sensor; determining whether the temperature of the stator assembly has reached a target temperature; in response to determining that the temperature of the stator assembly is equal to the target temperature, heating the stator assembly using the induction heating element to maintain the temperature of the stator assembly at the target temperature for a predetermined amount of time; determining whether the temperature of the stator assembly is equal to the final target temperature; in response to determining that the target temperature is not equal to the final target temperature, increasing the target temperature by a predetermined amount of degrees.

Abstract: A method of engaging wire ends of a stator assembly. The method involves advancing multiple fingers radially inwardly toward the wire ends, and rotating the fingers. The fingers have protrusions that engage the wire ends. A tooling assembly for engaging the wire ends has a first plate, a second plate, and has the fingers. The first plate has slots, and the second plate has teeth. The fingers have pins that ride in the slots of the first plate, and the fingers have teeth that mesh with the teeth of the second plate.

Abstract: A method of engaging wire ends of a stator assembly. The method involves advancing multiple fingers radially inwardly toward the wire ends, and rotating the fingers. The fingers have protrusions that engage the wire ends. A tooling assembly for engaging the wire ends has a first plate, a second plate, and has the fingers. The first plate has slots, and the second plate has teeth. The fingers have pins that ride in the slots of the first plate, and the fingers have teeth that mesh with the teeth of the second plate.

Abstract: A bolt includes a body and a threaded portion formed on the body. The bolt further includes a phosphate base coat, which covers at least the body and is in direct contact with the body. The bolt also includes a PTFE overcoat, which substantially covers the phosphate base coat and is separated from the body of the bolt by the phosphate base coat.

Abstract: Described herein is the method and apparatus for determining frequency of an oscillator coupled with one or more analog devices, and for determining within-die or across-die variations in an analog property associated with the one or more analog devices, the determining based on the oscillator frequency. The analog property includes output signal swing, bandwidth, offset, gain, and delay line linearity and range. The one or more analog devices include input-output (I/O) buffer, analog amplifier, and delay line. The method further comprises updating a simulation model file based on the determining of the within-die and/or across-die variations of the analog property.

Abstract: Described herein is the method and apparatus for determining frequency of an oscillator coupled with one or more analog devices, and for determining within-die or across-die variations in an analog property associated with the one or more analog devices, the determining based on the oscillator frequency. The analog property includes output signal swing, bandwidth, offset, gain, and delay line linearity and range. The one or more analog devices include input-output (I/O) buffer, analog amplifier, and delay line. The method further comprises updating a simulation model file based on the determining of the within-die and/or across-die variations of the analog property.

Abstract: Described herein is the method and apparatus for determining frequency of an oscillator coupled with one or more analog devices, and for determining within-die or across-die variations in an analog property associated with the one or more analog devices, the determining based on the oscillator frequency. The analog property includes output signal swing, bandwidth, offset, gain, and delay line linearity and range. The one or more analog devices include input-output (I/O) buffer, analog amplifier, and delay line. The method further comprises updating a simulation model file based on the determining of the within-die and/or across-die variations of the analog property.

Abstract: Described herein is the method and apparatus for determining frequency of an oscillator coupled with one or more analog devices, and for determining within-die or across-die variations in an analog property associated with the one or more analog devices, the determining based on the oscillator frequency. The analog property includes output signal swing, bandwidth, offset, gain, and delay line linearity and range. The one or more analog devices include input-output (I/O) buffer, analog amplifier, and delay line. The method further comprises updating a simulation model file based on the determining of the within-die and/or across-die variations of the analog property.

Abstract: A method and apparatus for an integrated circuit having a offset reference circuit block to receive an external voltage reference and output an offset reference voltage are described herein.

Abstract: A system and method for processing signals determines rise and fall times of a driving signal, compares the rise and fall times to desired values, and independently controls the rise and fall times to equal the desired values. The rise and fall times may be controlled by generating one or more first correction bits based on a difference between the rise time and a corresponding one of the desired values, generating one or more second correction bits based on a difference between the fall time and a corresponding one of the desired values, and then separately applying the bits to independently control the rise and fall times of the driving signal. The driving signal may be an I/O signal or another type of signal.

Abstract: A system and method for processing signals determines rise and fall times of a driving signal, compares the rise and fall times to desired values, and independently controls the rise and fall times to equal the desired values. The rise and fall times may be controlled by generating one or more first correction bits based on a difference between the rise time and a corresponding one of the desired values, generating one or more second correction bits based on a difference between the fall time and a corresponding one of the desired values, and then separately applying the bits to independently control the rise and fall times of the driving signal. The driving signal may be an I/O signal or another type of signal.

Abstract: A CMOS amplifier for optoelectronic receivers, the amplifier comprises two transimpedance amplifiers and two differential amplifier latches. One of the two transimpedance amplifiers has an input port to receive a current signal, such as, for example, a current signal from a photodetector, and provides a output voltage indicative of the received current signal. The other of the two transimpedance amplifiers may be viewed as having no input signal, so that it provides a reference voltage. The two transimpedance amplifiers are in close proximity to each other, so that power supply noise is a common mode signal in the output voltages of the two transimpedance amplifiers. The differential amplifier latches reject the common mode signal by comparing the reference voltage to the output voltage, and provide output logic voltages indicative of binary hard decisions.

Abstract: A high bandwidth, single stage, low power cascode transimpedance amplifier for short haul optical links. In one embodiment, an input signal is fed into the source of a common-gate pMOSFET, the output signal is taken at the drain of the common-gate pMOSFET, and bias current is supplied by a pMOSFET and a nMOSFET biased in their triode regions.

Abstract: A CMOS amplifier for optoelectronic receivers, the amplifier comprises two transimpedance amplifiers and two differential amplifier latches. One of the two transimpedance amplifiers has an input port to receive a current signal, such as, for example, a current signal from a photodetector, and provides a output voltage indicative of the received current signal. The other of the two transimpedance amplifiers may be viewed as having no input signal, so that it provides a reference voltage. The two transimpedance amplifiers are in close proximity to each other, so that power supply noise is a common mode signal in the output voltages of the two transimpedance amplifiers. The differential amplifier latches reject the common mode signal by comparing the reference voltage to the output voltage, and provide output logic voltages indicative of binary hard decisions.

Abstract: A high bandwidth, single stage, low power cascode transimpedance amplifier for short haul optical links. In one embodiment, an input signal is fed into the source of a common-gate pMOSFET, the output signal is taken at the drain of the common-gate pMOSFET, and bias current is supplied by a pMOSFET and a nMOSFET biased in their triode regions.

Abstract: A high bandwidth, single stage, low power cascode transimpedance amplifier for short haul optical links. In one embodiment, an input signal is fed into the source of a common-gate pMOSFET, the output signal is taken at the drain of the common-gate pMOSFET, and bias current is supplied by a pMOSFET and a nMOSFET biased in their triode regions.

Abstract: A high bandwidth, single stage, low power cascode transimpedance amplifier for short haul optical links. In one embodiment, an input signal is fed into the source of a common-gate pMOSFET, the output signal is taken at the drain of the common-gate pMOSFET, and bias current is supplied by a pMOSFET and a nMOSFET biased in their triode regions.