Abstract: System and method for debugging a run-time reconfigurable processing arrangement. The processing arrangement includes a host process that hosts a run-time reconfiguration application program and a programmable logic device (PLD). The run-time reconfiguration program specifies a circuit design with references to core generators in a library, generates configuration data that implements the circuit design on the PLD, and configures the PLD with the configuration data. One of the core generators generates a breakpoint circuit that steps the PLD for a selected number of clock cycles. When the PLD is activated, the breakpoint circuit steps the PLD, and state information of one or more selected elements of the PLD is analyzed after stepping the PLD. Depending on the analysis, the breakpoint core generator is re-parameterized and the PLD reconfigured with a new breakpoint circuit to continue debugging.

Abstract: A system and method for developing a circuit design for a programmable logic device. A tool is provided for interactively modifying a configuration bitstream, downloading the bitstream to a programmable logic device (PLD), and reading back and displaying state information from the PLD. In one embodiment, the tool is command driven. Responsive to a first command, the tool implements a selected logic core from a library of run-time parameterizable logic cores in a configuration bitstream. The bitstream can be automatically downloaded to the PLD as part of the first command, or alternatively, using a separate command. A second command is available for applying a clock signal to the PLD. After application of the clock signal, the states of selected elements implemented by the logic core are reported.