Patents by Inventor Timothy Richard Feldman

Timothy Richard Feldman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110085367
    Abstract: A data storage system includes a plurality of memory devices for storing data. The plurality of memory devices is classified into a plurality of groups of memory devices. A control circuit is adapted to provide concurrent memory access operations to the plurality of memory devices. Each of a plurality of data channels is configured to provide a data path between the control circuit and one of the groups of memory devices. A plurality of switches is configured to connect and disconnect one of the memory devices in a select one of the groups of memory devices to one of the plurality of data channels and concurrently connect and disconnect another of the memory devices in the select group of memory devices to a different one of the plurality of data channels.
    Type: Application
    Filed: October 14, 2009
    Publication date: April 14, 2011
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Timothy Richard Feldman, Wayne Howard Vinson
  • Publication number: 20110087631
    Abstract: The disclosure is related to systems and methods of distributing data in devices with multiple storage entities. In a particular embodiment, a system is disclosed that includes multiple storage entities, with each storage entity having a sub-controller. A controller is communicatively coupled to each of the multiple storage entities. The controller is configured to send at least one of a respective copy of data or metadata associated with the respective copy of the data to each of the multiple storage entities. Upon receipt of the at least one of the respective copy of the data or the metadata associated with the respective copy of the data, each sub-controller provides storage competency information of the respective storage entity for the respective copy of the data. Upon receiving storage competency information for the multiple storage entities, the controller selects a particular one of the multiple storage entities and notifies the selected storage entity to store the respective copy of the data.
    Type: Application
    Filed: October 9, 2009
    Publication date: April 14, 2011
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Timothy Richard Feldman, Wayne Howard Vinson, Jonathan Williams Haines
  • Publication number: 20110082985
    Abstract: The present disclosure provides a method in a data storage system. The method includes defining a plurality of jobs for a command received from a host. Each of the plurality of jobs is associated with one or more of a plurality of data storage resources of the data storage system. The plurality of jobs have a defined order that is a function of addresses of data in the plurality of data storage resources. The method also includes issuing the plurality of jobs to the associated data storage resources and receiving information from the data storage resources for the plurality of jobs. The information is received by a controller of the data storage system for the jobs in an order that is different than the defined order. The method includes transmitting the received information to the host for the plurality of jobs in the defined order.
    Type: Application
    Filed: October 5, 2009
    Publication date: April 7, 2011
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Jonathan Williams Haines, Brett Alan Cook, Timothy Richard Feldman, Paul Michael Wiggins
  • Publication number: 20110075490
    Abstract: Data stripes and addressing for flash memory devices are provided. Flash memory devices illustratively have a plurality of programmable devices that are capable of simultaneously storing data. A plurality of erasure blocks are within each of the programmable devices, and each erasure block has pages of transistors. The flash memory devices are logically organized as a plurality of stripes. Each stripe has a height and a width. In an embodiment, the stripe height is greater than one page. In another embodiment, the stripe width is less than all of the programmable devices within the flash memory device.
    Type: Application
    Filed: September 29, 2009
    Publication date: March 31, 2011
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Luke William Friendshuh, Mark Allen Gaertner, Jonathan Williams Haines, Timothy Richard Feldman
  • Publication number: 20100325340
    Abstract: The disclosure is related to systems and methods of controlling wear of a memory. In a particular embodiment, a system is disclosed that comprises a memory and a performance governor circuit coupled to the memory. The performance governor circuit is adapted to control a wear of the memory as a function of time.
    Type: Application
    Filed: June 23, 2009
    Publication date: December 23, 2010
    Applicant: Seagate Technology LLC
    Inventors: Timothy Richard Feldman, Jonathan Williams Haines, Brett Alan Cook
  • Publication number: 20100302871
    Abstract: Methods and devices are provided for concurrent intersymbol interference encoding in a solid state memory. In an illustrative embodiment, a write data signal is received as input to a processing component. A channel-effect-corrected encoding of the write data signal is produced, where the channel-effect-corrected encoding is based on the write data signal and a channel effect factor that models concurrent intersymbol interference of the write data signal in a target data storage component in communicative connection with the processing component. An output signal based on the channel-effect-corrected encoding of the write data signal is produced from the processing component.
    Type: Application
    Filed: May 29, 2009
    Publication date: December 2, 2010
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Jonathan Williams Haines, Timothy Richard Feldman
  • Patent number: 7747907
    Abstract: A predictive failure control circuit and associated method are provided in a data storing and retrieving apparatus. The circuit is configured to schedule a data integrity operation on data associated with a subportion of a data storage space, in relation to a comparison of an accumulated plurality of executed host access commands associated with the subportion. The subportion can comprise a sector or a single track or a band of tracks. A table preferably stores accumulated number of host access commands for each of a plurality of subportions of the data storage space. The data integrity operation can comprise reading the data on to detect degradation and restoring the recovered data to the same or to new, different tracks. The data subportions can also be reallocated to a new location.
    Type: Grant
    Filed: September 20, 2005
    Date of Patent: June 29, 2010
    Assignee: Seagate Technology LLC
    Inventors: Edwin Scott Olds, Jonathan Williams Haines, Dan Joseph Coonen, Timothy Richard Feldman, Bruce Douglas Emo, James Joseph Touchton
  • Publication number: 20100153680
    Abstract: In a particular embodiment, a storage device includes a controller that is adapted to receive environmental data from a plurality of environmental sensors, where the environmental data is related to an operating environment of the storage device. Further, the controller is adapted to receive state information related to the data storage medium from a plurality of firmware detectors, to weight the received environmental data and the received state information according to a pre-determined weighting table, and to dynamically manage at least one attribute of the storage device based on the weighted environmental data and the weighted state information.
    Type: Application
    Filed: December 17, 2008
    Publication date: June 17, 2010
    Applicant: Seagate Technology LLC
    Inventors: Michael Edward Baum, Jim Joseph Touchton, Timothy Richard Feldman, Mike Montemorra
  • Publication number: 20090164742
    Abstract: Systems and methods of selective data mirroring are disclosed. In a particular embodiment, a device is disclosed that includes a data storage medium and a controller operably coupled to the data storage medium. The controller configured to selectively enable a data mirroring function to copy data in a first data storage location of the data storage medium to one or more second data storage locations of the data storage medium when the one or more second data storage locations do not have valid primary data stored to them.
    Type: Application
    Filed: December 20, 2007
    Publication date: June 25, 2009
    Applicant: SEAGATE TECHNOLOGY, LLC.
    Inventors: JOSEPH L. WACH, TIMOTHY RICHARD FELDMAN
  • Publication number: 20090002863
    Abstract: Systems and methods of monitoring data operations at a data storage device are disclosed. In an embodiment, a first read access request to access first data and a second read access request to access second data may be determined. A first physical block address containing the first data and a second physical block address containing the second data may be determined. The first physical block address and the second physical block address may not be located contiguously. The first data and the second data may be stored in contiguous physical block addresses.
    Type: Application
    Filed: June 29, 2007
    Publication date: January 1, 2009
    Applicant: SEAGATE TECHNOLOGY, LLC
    Inventors: Timothy Richard Feldman, Edwin Scott Olds
  • Publication number: 20080313396
    Abstract: Systems and methods of monitoring logical block address (LBA) activity are disclosed. In an embodiment, a pattern of a data storage device may be monitored. An LBA may be detected that is accessed based on the pattern. The LBA may be added to a list of LBAs stored in a memory.
    Type: Application
    Filed: June 15, 2007
    Publication date: December 18, 2008
    Applicant: SEAGATE TECHNOLOGY, LLC
    Inventors: Timothy Richard Feldman, Edwin Scott Olds, Jonathan Williams Haines, Daniel Joseph Coonen
  • Patent number: 6324633
    Abstract: A cache system and method for configuring and accessing a cache that enables a binary-sized memory space to be efficiently shared amongst cache and non-cache uses. A storage device is provided having a plurality of blocks where each block is identified with a block address. An access request identifies a target block address. The target block address includes an upper portion and a lower portion. A non-binary divide is performed on the upper portion to produce a quotient and a remainder. The remainder portion is combined with the lower portion to create an index. The index is applied to a tag memory structure to select an entry or set of entries in the tag memory structure. The content of the selected entry is compared to the quotient portion to determine if the target block is represented in the cache.
    Type: Grant
    Filed: December 29, 1999
    Date of Patent: November 27, 2001
    Assignee: STMicroelectronics, Inc.
    Inventors: Lance Leslie Flake, Timothy Richard Feldman