Patents by Inventor TIMOTHY ROWLEY

TIMOTHY ROWLEY has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11501484
    Abstract: Apparatus and method for acceleration data structure refit. For example, one embodiment of an apparatus comprises: a ray generator to generate a plurality of rays in a first graphics scene; a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes including inner nodes and leaf nodes stored in a memory in a depth-first search (DFS) order; traversal hardware logic to traverse one or more of the rays through the acceleration data structure; intersection hardware logic to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; a node refit unit comprising circuitry and/or logic to read consecutively through at least the inner nodes in the memory in reverse DFS order to perform a bottom-up refit operation on the hierarchical acceleration data structure.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: November 15, 2022
    Assignee: INTEL CORPORATION
    Inventors: Michael Apodaca, Carsten Benthin, Kai Xiao, Carson Brownlee, Timothy Rowley, Joshua Barczak, Travis Schluessler
  • Publication number: 20220103597
    Abstract: A network optimization controller (NOC) performs operations including obtaining, from a secure access service edge (SASE) device executing a security service, a first data set defining a security performance metric provided by the security service, and obtaining, from the SASE, a second data set defining a network performance metric associated with a network device. The operations further include defining a policy based at least in part on the first data set and the second data set, determining if the policy has been violated, and changing a first access modality provided for the network device to access an end host to a second access modality based at least in part on the policy being violated. The first access modality and the second access modality define different methods of access to the end host.
    Type: Application
    Filed: September 29, 2020
    Publication date: March 31, 2022
    Inventors: Yeneneh Elfaged Gobena, Hazim Hashim Dahir, Timothy Rowley, Ibrahim Amir Darwish
  • Patent number: 10937225
    Abstract: Apparatus and method including cell primitive for unstructured volume rendering. For example, one embodiment of an apparatus comprises: a ray generator to generate a plurality of rays in a first graphics scene; a hierarchical acceleration data structure generator to construct a hierarchical acceleration data structure comprising a plurality of hierarchically arranged nodes including leaf nodes and inner nodes; traversal circuitry to traverse one or more of the rays through the hierarchical acceleration data structure; unstructured volume intersection circuitry to intersect a ray with an unstructured volume primitive within a leaf node of the hierarchical acceleration data structure, the unstructured volume intersection circuitry to determine multiple intersection hits between a ray and an unstructured volume primitive.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: March 2, 2021
    Assignee: Intel Corporation
    Inventors: Timothy Rowley, Won-Jong Lee, Karol Szerszen, Hiroshi Akiba, Alexey Supikov
  • Publication number: 20210012553
    Abstract: Apparatus and method for acceleration data structure refit. For example, one embodiment of an apparatus comprises: a ray generator to generate a plurality of rays in a first graphics scene; a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes including inner nodes and leaf nodes stored in a memory in a depth-first search (DFS) order; traversal hardware logic to traverse one or more of the rays through the acceleration data structure; intersection hardware logic to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; a node refit unit comprising circuitry and/or logic to read consecutively through at least the inner nodes in the memory in reverse DFS order to perform a bottom-up refit operation on the hierarchical acceleration data structure.
    Type: Application
    Filed: September 25, 2020
    Publication date: January 14, 2021
    Inventors: Michael APODACA, Carsten BENTHIN, Kai XIAO, Carson BROWNLEE, Timothy ROWLEY, Joshua BARCZAK, Travis SCHLUESSLER
  • Publication number: 20200211267
    Abstract: Apparatus and method including cell primitive for unstructured volume rendering. For example, one embodiment of an apparatus comprises: a ray generator to generate a plurality of rays in a first graphics scene; a hierarchical acceleration data structure generator to construct a hierarchical acceleration data structure comprising a plurality of hierarchically arranged nodes including leaf nodes and inner nodes; traversal circuitry to traverse one or more of the rays through the hierarchical acceleration data structure; unstructured volume intersection circuitry to intersect a ray with an unstructured volume primitive within a leaf node of the hierarchical acceleration data structure, the unstructured volume intersection circuitry to determine multiple intersection hits between a ray and an unstructured volume primitive.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 2, 2020
    Inventors: TIMOTHY ROWLEY, WON-JONG LEE, KAROL SZERSZEN, HIROSHI AKIBA, ALEXEY SUPIKOV
  • Publication number: 20200211259
    Abstract: Apparatus and method for acceleration data structure refit. For example, one embodiment of an apparatus comprises: a ray generator to generate a plurality of rays in a first graphics scene; a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes including inner nodes and leaf nodes stored in a memory in a depth-first search (DFS) order; traversal hardware logic to traverse one or more of the rays through the acceleration data structure; intersection hardware logic to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; a node refit unit comprising circuitry and/or logic to read consecutively through at least the inner nodes in the memory in reverse DFS order to perform a bottom-up refit operation on the hierarchical acceleration data structure.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 2, 2020
    Inventors: MICHAEL APODACA, CARSTEN BENTHIN, KAI XIAO, CARSON BROWNLEE, TIMOTHY ROWLEY, JOSHUA BARCZAK, TRAVIS SCHLUESSLER