Abstract: A system and method for distributing data in a system. The system comprises a control register logic circuits located at scattered locations in the system, where a location is defined as scattered if the propagation delay of data sent from the control register is more than approximately one clock period. The system also comprises one or more shift registers coupled to the control register and the logic circuits. A section of each shift register is placed in proximity to each logic circuit and data is shifted serially from the control register through the shift registers to the logic circuits. A synchronizer circuit is coupled to the shift registers to synchronize data arriving at each section of the shift registers with a shift control signal arriving at the same section of the shift register.

Abstract: A system and method for distributing data in a system. The system comprises a control register logic circuits located at scattered locations in the system, where a location is defined as scattered if the propagation delay of data sent from the control register is more than approximately one clock period. The system also comprises one or more shift registers coupled to the control register and the logic circuits. A section of each shift register is placed in proximity to each logic circuit and data is shifted serially from the control register through the shift registers to the logic circuits. A synchronizer circuit is coupled to the shift registers to synchronize data arriving at each section of the shift registers with a shift control signal arriving at the same section of the shift register.

Abstract: Error reporting circuitry interrupts the CPU on the occurrence of a single bit memory error only when the chip member causing the error is different from the chip number that caused the previous error.