Abstract: Techniques to generate driving scenarios for autonomous vehicles characterize a path in a driving scenario according to metrics such as narrowness and effort. Nodes of the path are assigned a time for action to avoid collision from the node. The generated scenarios may be simulated in a computer.

Abstract: A computer system includes a processor core and a memory system in signal communication with the processor core. The memory system includes a first cache and a second cache. The first cache is arranged at a first level of a hierarchy in the memory system and is configured to store a plurality of first-cache entries. The second cache is arranged at a second level of the hierarchy that is lower than the first level, and stores a plurality of second-cache entries. The first cache maintains a directory that contains information for each of the first-cache entries. The second cache maintains a shadow pointer directory (SPD) that includes one or more SPD entries that maps each of the first-cache entries to a corresponding second cache entry at a lower-level cache location.

Abstract: Embodiments are for processor cross-core cache line contention management. A computer-implemented method includes sending a cross-invalidate command to one or more caches based on receiving a cache state change request for a cache line in a symmetric multiprocessing system and determining a retry delay based on receiving a cross-invalidate reject response from at least one of the one or more caches. The computer-implemented method also includes waiting until a retry delay period associated with the retry delay has elapsed to resend the cross-invalidate command to the one or more caches and granting the cache state change request for the cache line based on receiving a cross-invalidate accept response from the one or more caches.

Abstract: A lower-level cache managing cross-core invalidation (XI) snapshots in a shared-memory multiprocessing system, wherein the management of XI snapshots reduces an amount of required snapshots while allowing shared lower-level caches, comprising: the lower-level cache maintaining respective response sync state for at least one processor in a plurality of processors signifying that a line may have been changed by another processor since last fetched by a requesting processor.

Abstract: An estimation model utilizes simulations of an autonomous vehicle and objects detected near the automated vehicle to develop estimates of tolerable frame processing latency to develop real world frame processing latency estimates for similar driving conditions. An estimation model can a minimum tolerable latency for processing the frames of image data of an object detection camera on an autonomous vehicle using the object state data of the objects detected near the autonomous vehicle. An autonomous vehicle system process can determine if the processing latency of a sensor is greater than the modeled tolerable latency for that sensor, then a safety check is failed and an alert is sent. An autonomous vehicle system process can determine if the processing latency of a sensor is greater than the modeled tolerable latency for that sensor, then the hardware resources are prioritized to the processing for that sensor.

Abstract: Techniques to generate driving scenarios for autonomous vehicles characterize a path in a driving scenario according to metrics such as narrowness and effort. Nodes of the path are assigned a time for action to avoid collision from the node. The generated scenarios may be simulated in a computer.

Abstract: Techniques to generate driving scenarios for autonomous vehicles characterize a path in a driving scenario according to metrics such as narrowness and effort. Nodes of the path are assigned a time for action to avoid collision from the node. The generated scenarios may be simulated in a computer.

Abstract: An error reporting system utilizes a parity checker to receive data results from execution of an original instruction and a parity bit for the data. A decoder receives an error correcting code (ECC) for data resulting from execution of a shadow instruction of the original instruction, and data error correction is initiated on the original instruction result on condition of a mismatch between the parity bit and the original instruction result, and the decoder asserting a correctable error in the original instruction result.

Abstract: An error reporting system utilizes a parity checker to receive data results from execution of an original instruction and a parity bit for the data. A decoder receives an error correcting code (ECC) for data resulting from execution of a shadow instruction of the original instruction, and data error correction is initiated on the original instruction result on condition of a mismatch between the parity bit and the original instruction result, and the decoder asserting a correctable error in the original instruction result.

Abstract: Techniques to characterize driving scenarios for autonomous vehicles characterize a path in a driving scenario according to metrics such as narrowness and effort. The scenarios may be characterized using a tree-based or tensor-based approach.

Abstract: Techniques to generate driving scenarios for autonomous vehicles characterize a path in a driving scenario according to metrics such as narrowness and effort. Nodes of the path are assigned a time for action to avoid collision from the node. The generated scenarios may be simulated in a computer.

Abstract: Techniques to characterize driving scenarios for autonomous vehicles characterize a path in a driving scenario according to metrics such as narrowness and effort. The scenarios may be characterized using a tree-based or tensor-based approach.

Abstract: A thread execution method in a processor includes executing original instructions of a first thread in a first execution lane of the processor, and interleaving execution of duplicated instructions of the first thread with execution of original instructions of a second thread in a second execution lane of the processor.

Abstract: Software-only and software-hardware optimizations to reduce the overhead of intra-thread instruction duplication on a GPU or other instruction processor are disclosed. The optimizations trade off error containment for performance and include ISA extensions with limited hardware changes and area costs.

Abstract: An error reporting system utilizes a parity checker to receive data results from execution of an original instruction and a parity bit for the data. A decoder receives an error correcting code (ECC) for data resulting from execution of a shadow instruction of the original instruction, and data error correction is initiated on the original instruction result on condition of a mismatch between the parity bit and the original instruction result, and the decoder asserting a correctable error in the original instruction result.

Abstract: A family of software-hardware cooperative mechanisms to accelerate intra-thread duplication leverage the register file error detection hardware to implicitly check the data from duplicate instructions, avoiding the overheads of instruction checking and enforcing low-latency error detection with strict error containment guarantees.

Abstract: A family of software-hardware cooperative mechanisms to accelerate intra-thread duplication leverage the register file error detection hardware to implicitly check the data from duplicate instructions, avoiding the overheads of instruction checking and enforcing low-latency error detection with strict error containment guarantees.

Abstract: Software-only and software-hardware optimizations to reduce the overhead of intra -thread instruction duplication on a GPU or other instruction processor are disclosed. The optimizations trade off error containment for performance and include ISA extensions with limited hardware changes and area costs.

Abstract: Approaches for retrieving files from a replicated file system. A component receives, from a requestor, a request for a copy of a data unit. The component identifies a plurality of storage nodes that each stores a complete copy of the data unit. The component sends, to the plurality of storage nodes, an instruction to retrieve a copy of the data unit within a specified period of time. At each storage node receiving an instruction, a determination of whether the copy of the data unit may be retrieved within the specified period of time is made, and if so, the copy of the data unit is provided to the component only if the copy of the data unit was actually retrieved within the specified period. The component provides the first copy of the data unit it receives to the requestor and discards any subsequently received copies of the data unit.

Abstract: A method and a storage system are provided for implementing a sustained large block random write performance mechanism for shingled magnetic recording (SMR) drives in a redundant array of inexpensive disks (RAID). A Solid State Drive (SSD) is provided with the SMR drives in the RAID. The SSD is used in a hot spare mode, which is activated when a large block random-write event is identified for a SMR drive in the RAID. In the hot spare mode, the SSD temporarily receives new incoming writes for the identified SMR drive. Then the identified SMR drive is updated from the SSD to restore the state of the identified SMR drive, and operations continue with normal writing only using the SMR drives in the RAID.