Abstract: An apparatus and method for programming a universal remote control. The method includes receiving a transmitted signal of unknown modulation technique from a native remote control and characterizing the received signal in parameters of a pre-determined modulation technique.

Abstract: Analog and digital video signals are each representative of a picture and each may carry program guide information. A demultiplexer has the digital video signal as an input and the program guide information as an output. A demodulator has at least a luminance component of the analog video signal as an input and the program guide information as an output. A microprocessor, a video graphics adapter, the demultiplexer and the demodulator are interconnected by a data bus. Either of the program guide outputs is transferable to the video graphics adapter, which formats a graphics video signal representative of the program guide information. The graphics video signal and a selected one of the video signals are inputs to a multiplexer, which outputs a combined video signal representative of both the program guide information and the picture represented by the selected video signal.

Abstract: A subtractor (106) forms a difference signal (D) from a video input signal (C) and a further signal (M) supplied thereto. The difference signal is limited (108) and attenuated (110) and the resultant signal (F) is combined (112) with the video input signal for providing a noise reduced video output signal (H). A delay circuit (202), responsive to the video output signal, provides field (A) and frame (B) delayed video signals. A selection circuit (220) selects a median value (M) of the field delayed video signal, the frame delayed video signal and the video input signal as the further signal for application to the subtractor. Advantageously, the further signal provides the dual functions of (1) facilitating the noise reduction of the output signal and (2) concurrently reducing the occurrence of potential motion artifacts to a very substantial degree.

Abstract: In a synchronizing circuit, an oscillator provides an output signal at a frequency that is a higher integral multiple than that of a synchronizing input signal. A control circuit, responsive to the input signal and a feedback signal representative of the output signal, generates a control signal that is indicative of a difference in phase or frequency between the input and output signals. The oscillator is responsive to the control signal for synchronized tracking of the output signal to the input signal. The control signal exhibits a periodic variation which tends to result in a deviation of the oscillator output signal from its synchronized tracking condition in accordance with the periodic variation. The phase of the output signal is offset relative to a corresponding phase of the periodic variation of the control signal for counteracting this deviation.

Abstract: A video control system, comprises a deflection system having a dimensionally adjustable raster, a circuit for detecting a letterbox video signal source and a circuit for dimensionally controlling the raster of the deflection system responsive to the detecting circuit. The detecting circuit and the control circuit are operable automatically. The detection circuit can comprise a circuit for measuring video luma levels of the video signal source in at least two regions of each video field and a circuit for comparing the luma levels from each of the regions to respective threshold levels. In an alternative, the detection circuit comprises a circuit for comparing respective minimum and maximum luminance values for a plurality of successive video lines, a circuit for storing minimum and maximum luminance values for the plurality of video lines, a circuit for generating gradients indicative of the stored values and a circuit for comparing the gradients to threshold values.

Abstract: A video display for a television apparatus has a wide format display ratio and is synchronized with a first video signal representative of first picture. A PIP processor is responsive to a second video signal representative of a second picture to define an auxiliary picture smaller in size than the video display. A FIFO line memory stores successive lines of video information representative of the auxiliary picture, which are combined with certain successive lines of video information representative of the first picture. A counter initialized at a time corresponding to the start of each horizontal line of the first video signal generates a variable time delay. A FIFO control circuit successively initiates a transfer of the lines of video information representative of the auxiliary picture from the line memory for combination with the video information representative of the main picture after the variable time delay.

Abstract: A picture overlay system assures proper size and placement of picture overlays in simultaneous picture displays. The system comprises a video memory and a control circuit for writing and reading information from a video signal into and out of the video memory, the information relating to video data and field type. A reading circuit supplies information from the video memory synchronously with a display for another video signal. An interpolator selectively compresses and expands the information read from the reading circuit. The field type information undergoes the compression and expansion together with the video information. A decoding circuit decodes the field type information to identify first and second types of fields and an absence of valid video data. A multiplexer combines the video signals for simultaneous display, operating responsive to the decoding circuit.

Abstract: A video display system comprises: a video display; first and second signal processors for cropping first and second video signals representative of first and second pictures; a circuit for generating a side-by-side display format of the pictures on the video display; and, a panning control circuit, responsive to panning command signals, for positioning said pictures in the side-by-side display format and for independently panning the pictures, as positioned. The panning control circuit generates independent fixed and variable delays for controlling line memories in the signal processors. Fixed delays control picture positions and variable delays control panning.

Abstract: A circuit for compressing and expanding video color component data comprises a FIFO line memory and a delay circuit. A timing circuit generates control signals for writing data into the line memory and for reading data from the line memory to compress and expand the data. The delay circuit matches the data compressed or expanded in the FIFO line memory to luminance data which is similarly compressed or expanded. A switching network selectively establishes a first signal path in which the line memory precedes the delay circuit for implementing the data expansion and a second signal path in which the delay circuit precedes the line memory for implementing the data compression. The switching network is controlled according to selected display formats requiring compression or expansion, for example by a microprocessor.

Abstract: A two stage interpolation system provides greater bandwidth for signals compressed and expanded by interpolation, for example video signals displayed in a zoom or enlarged mode. A finite impulse response filter generates from a first signal of digital samples a second signal of digital samples representing signal points between the samples of the first signal. The first signal is delayed, but otherwise substantially unmodified. The second signal and the delayed first signal are interleaved, for example by a multiplexer, to produce a third signal of digital values having a sample density twice that of the first signal. A compensated variable interpolator derives from the third signal a fourth signal of digital samples in which the frequency content of information represented by the first signal has been changed.

Abstract: A video display control system comprises: a video display having a wide format display ratio; a letterbox detector for sampling video information in pictures represented by input video signals having a letterbox format and generating a control signal for enlarging the pictures for substantially filling the video display means with active video, the letterbox format pictures sometimes having auxiliary information disposed in a border area; and, a circuit for preventing the letterbox detector from sampling the video information in any portion of the border area in which the auxiliary information can be expected to be disposed, when present. In the case of logos, which are generally disposed near or at the right side of the lower border, a horizontal sampling range will exclude the right side of each horizontal line.

Abstract: Video luminance data from a video signal is selectably compressed and expanded in a first signal path including a first line memory. A second line memory in a parallel signal path processes video chrominance data from the video signal. A control circuit generates respective timing signals for writing data into each of the first and second memories and for reading data from each of first and second the line memories. A timing delay circuit for the control circuit, has video compression and expansion modes of operation. During the compression mode, reading of the second line memory is delayed relative to writing of the second line memory. During the expansion mode, writing of the first line memory is delayed relative to writing of the second line memory or reading of the second line memory is delayed relative to writing of the second line memory. The duration of the timing delays can be selected from a range of values.

Abstract: A video display control system comprises: a video display having a wide format display ratio; a letterbox detector for sampling video information in pictures represented by input video signals having a letterbox format and generating a control signal for enlarging the pictures for substantially filling the video display means with active video; and, a first control circuit for restricting operation of the letterbox detector to a vertical range of horizontal lines in each field of the video signal; and, a second control circuit for restricting operation of the letterbox detector to a horizontal range of video data in each of the horizontal lines.

Abstract: A picture overlay system assures proper image aspect ratios for picture overlays. The system comprises a video memory and a control circuit for writing and reading information from a video signal into and out of the video memory, the information relating to video data. A reading circuit supplies information from the video memory synchronously with a display for another video signal. An interpolator selectively compresses and expands the information read from the reading circuit, independently of any other processing which might vertically compress or expand said video data. A multiplexer combines the video signals for simultaneous display. The reading circuit can comprise an asynchronous line memory for the information read from the video memory, having a write port operable synchronously with the reading of the video memory and a read port operable synchronously with the display for the other video signal.

Abstract: A circuit for compressing and expanding video data comprises a FIFO line memory and an interpolator. A timing circuit generates control signals for writing data into the line memory and for reading data from the line memory to compress and expand the data. The interpolator smooths the data expanded or to be compressed in the FIFO line memory. A switching network selectively establishes a first signal path in which the line memory precedes the interpolator for implementing the data expansion and a second signal path in which the interpolator precedes the line memory for implementing the data compression. The switching network is controlled according to selected display formats requiring compression or expansion, for example by a microprocessor.

Abstract: A video display control system automatically controls a video display responsive to detection of letterbox format input video signals having varying format display ratios. A detection circuit continuously detects the first and last lines of active video in a video signal. A memory stores scan line numbers corresponding to the first and last lines of active video. The height of the picture is determined from the scan line numbers of the first and last lines of active video. The picture height is indicative of the format display ratio of the letterbox input. A comparator circuit compares the picture height to a threshold corresponding to the widest expected format display ratio of a letterbox input signal.

Abstract: A video display control system comprises a display for the video signal, a vertical zoom circuit for generating from the video signal a picture having a vertical height greater than the display, and, a vertical panning circuit for displaying a selected portion of the picture on the display by generating a time delay relative to a vertical synchronizing component of the video signal. A counter and comparator measure the respective durations of successive fields of the video signal and the time delay. A circuit responsive to the comparing means generates a first signal for initiating delayed reset pulses when a field of the video signal and the time delay match in duration. Another circuit generates a second signal for initiating the delayed reset pulses in accordance with the vertical synchronizing component. A gating circuit selects the first initiating signal as an output, if present, and selects the second initiating signal as an output absent detection of the first initiating signal.

Abstract: A television apparatus includes a display for a video signal representing a picture. The video signal has a vertical synchronizing component defining fields of horizontal lines which can have other than a standard number of horizontal lines per field under certain operating conditions. A counter measures the number of horizontal lines in each field. A panning circuit generates a vertical reset signal which is phase shifted by a selected number of horizontal lines relative to the vertical synchronizing component of the video signal for vertically panning the picture on the video display by the selected number of horizontal lines. The selected number of horizontal lines is adjusted responsive to the measured lengths of the fields to maintain the selected amount of vertical panning even under the certain operating conditions.

Abstract: A line memory and control system comprises a line memory, for example a first in first out (FIFO) device. A comparator compares a first value, specifying a location in the horizontal line period where reading or writing of the line memory is to begin, with a second value, fixing pixel location within each line period. A register stores the number of data samples stored in the line memory. A counter counts the number of data samples which have actually been written into the line memory or read from the line memory. The counter has an output of the comparator as a first input and the number of data samples previously stored in the line memory as a second input. In the case of both compression and expansion, a line memory control system assures that the number of samples written into each FIFO line memory be the same as the number of samples read out of each FIFO line memory.

Abstract: A video display unit and deflection system are synchronized with a first video signal. A detecting circuit determines whether the first video signal has more than one field type. A second video signal has more than one field type. A multiplexer combines the first and a second video signals for a simultaneous video display. A video signal processor is responsive to the detecting circuit and has two modes of operation. In a first mode of operation, when the first video signal has more than one field type, all fields of the second video signal are an output to the multiplexer. In a second mode of operation, when the first video signal has only one field type, only one field type of the second video signal is an output to the multiplexer. The video signal processor has a memory for storing the second video signal. Only one field type of the video signal is written into and read from the memory during the second mode of operation.