Patents by Inventor Timothy Wig
Timothy Wig has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11599497Abstract: A device includes a receiver to receive one or more training sequences during a training of a link, where the link connects two devices. The device may include agent logic to determine, from the one or more training sequences, a number of extension devices on the link between the two devices, and determine that the number of extension devices exceeds a threshold number. The device may include a transmitter to send a plurality of clock compensation ordered sets on the link based on determining that the number of extension devices exceeds a threshold number.Type: GrantFiled: August 31, 2020Date of Patent: March 7, 2023Assignee: Intel CorporationInventors: Zuoguo Wu, Debendra Das Sharma, Mohiuddin M. Mazumder, Jong-Ru Guo, Anupriya Sriramulu, Narasimha Lanka, Timothy Wig, Jeff Morriss
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Patent number: 11569617Abstract: A system board is provided that includes a connector. The connector includes a pinfield. The pinfield includes a set of differential signal conductors to correspond to pins of a set of differential signaling pairs; a set of one or more auxiliary signal conductors to carry auxiliary signals; and a plurality of thru-hole ground vias adjacent to a particular one of the auxiliary signal conductors in the set of auxiliary signal conductors.Type: GrantFiled: October 19, 2020Date of Patent: January 31, 2023Assignee: Intel CorporationInventor: Timothy Wig
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Publication number: 20210036464Abstract: A system board is provided that includes a connector. The connector includes a pinfield. The pinfield includes a set of differential signal conductors to correspond to pins of a set of differential signaling pairs; a set of one or more auxiliary signal conductors to carry auxiliary signals; and a plurality of thru-hole ground vias adjacent to a particular one of the auxiliary signal conductors in the set of auxiliary signal conductors.Type: ApplicationFiled: October 19, 2020Publication date: February 4, 2021Applicant: Intel CorporationInventor: Timothy Wig
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Publication number: 20200394151Abstract: A device includes a receiver to receive one or more training sequences during a training of a link, where the link connects two devices. The device may include agent logic to determine, from the one or more training sequences, a number of extension devices on the link between the two devices, and determine that the number of extension devices exceeds a threshold number. The device may include a transmitter to send a plurality of clock compensation ordered sets on the link based on determining that the number of extension devices exceeds a threshold number.Type: ApplicationFiled: August 31, 2020Publication date: December 17, 2020Applicant: Intel CorporationInventors: Zuoguo Wu, Debendra Das Sharma, Mohiuddin M. Mazumder, Jong-Ru Guo, Anupriya Sriramulu, Narasimha Lanka, Timothy Wig, Jeff Morriss
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Patent number: 10804631Abstract: A device includes a circuit board with circuit components, and first edge finger tab extending from the circuit board, and a second edge finger tab extending from the circuit board. The first edge finger tab includes electrical contacts to provide signaling to and from particular circuit components of the circuit board, and is to mate with a Peripheral Component Interconnect Express (PCIe)-compatible edge card connection mechanism of a baseboard. The second edge finger tab includes electrical contacts to provide power delivery to the circuit board, is to mate with a second edge card connection mechanism of the baseboard. In some aspects, the second edge finger tab may be a PCIe-compatible feature that is typically to prevent the device from being inserted into a legacy PCI edge card connection mechanism, or with a PCIe-compatible feature that is typically to engage a retention mechanism of a baseboard.Type: GrantFiled: June 10, 2019Date of Patent: October 13, 2020Assignee: Intel CorporationInventors: Timothy Wig, Manisha M. Nilange, Thane M. Larson, Horthense Delphine Tamdem
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Patent number: 10789201Abstract: A device includes a receiver to receive one or more training sequences during a training of a link, where the link connects two devices. The device may include agent logic to determine, from the one or more training sequences, a number of extension devices on the link between the two devices, and determine that the number of extension devices exceeds a threshold number. The device may include a transmitter to send a plurality of clock compensation ordered sets on the link based on determining that the number of extension devices exceeds a threshold number.Type: GrantFiled: June 29, 2017Date of Patent: September 29, 2020Assignee: Intel CorporationInventors: Zuoguo Wu, Debendra Das Sharma, Mohiuddin M. Mazumder, Jong-Ru Guo, Anupriya Sriramulu, Narasimha Lanka, Timothy Wig, Jeff Morriss
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Publication number: 20190296470Abstract: A device includes a circuit board with circuit components, and first edge finger tab extending from the circuit board, and a second edge finger tab extending from the circuit board. The first edge finger tab includes electrical contacts to provide signaling to and from particular circuit components of the circuit board, and is to mate with a Peripheral Component Interconnect Express (PCIe)-compatible edge card connection mechanism of a baseboard. The second edge finger tab includes electrical contacts to provide power delivery to the circuit board, is to mate with a second edge card connection mechanism of the baseboard. In some aspects, the second edge finger tab may be a PCIe-compatible feature that is typically to prevent the device from being inserted into a legacy PCI edge card connection mechanism, or with a PCIe-compatible feature that is typically to engage a retention mechanism of a baseboard.Type: ApplicationFiled: June 10, 2019Publication date: September 26, 2019Applicant: Intel CorporationInventors: Timothy Wig, Manisha M. Nilange, Thane M. Larson, Horthense Delphine Tamdem
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Publication number: 20180276176Abstract: Embodiments are directed to systems and device that include a printed circuit board (PCB) and a through-hole pin-field. The pin-field includes a plurality of ground through-holes arranged along a centerline; a plurality of ground pins, each of the plurality of ground pins coupled to a corresponding ground through-hole; a first signal though-hole arranged on a first side of the centerline; a second signal through-hole arrange on a second side of the centerline, the first side oppose the second side; a first signal pin electrically connected to the PCB through the first signal through-hole, the first signal pin comprising a bend in a first direction and disposed proximate the first through-hole; and a second signal pin electrically connected to the PCB through the second signal through-hole, the second signal pin comprising a bend in a second direction opposite the first direction and disposed proximate the second through-hole.Type: ApplicationFiled: July 3, 2017Publication date: September 27, 2018Applicant: Intel CorporationInventors: Timothy Wig, Umair I. Khan
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Publication number: 20180253398Abstract: A device includes a receiver to receive one or more training sequences during a training of a link, where the link connects two devices. The device may include agent logic to determine, from the one or more training sequences, a number of extension devices on the link between the two devices, and determine that the number of extension devices exceeds a threshold number. The device may include a transmitter to send a plurality of clock compensation ordered sets on the link based on determining that the number of extension devices exceeds a threshold number.Type: ApplicationFiled: June 29, 2017Publication date: September 6, 2018Inventors: Zuoguo Wu, Debendra Das Sharma, Mohiuddin M. Mazumder, Jong-Ru Guo, Anupriya Sriramulu, Narasimha Lanka, Timothy Wig, Jeff Morriss
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Patent number: 9660364Abstract: An electronic device for transmitting data is described herein. In some examples, the electronic device includes a package substrate, and a plurality of integrated circuits to be coupled to the package substrate, at least one integrated circuit comprising a topside connector or an edge connector to be coupled to a cable that is to couple to a cable receptacle.Type: GrantFiled: October 16, 2013Date of Patent: May 23, 2017Assignee: Intel CorporationInventors: Timothy Wig, Todd Hinck, Sanka Ganesan
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Patent number: 9559445Abstract: Techniques for manufacturing an add-in card are described. An example of an add-in card in accordance with the described techniques includes a circuit board with contact fingers formed on an outer surface of the circuit board. Each of the contact fingers is configured to make electrical contact with a pin when inserted into a receptacle. The gap between the contact fingers is greater than or equal to a width of the pin. The add-in card also includes a protection mechanism to prevent the pin from being captured between the contact fingers if the add-in card is misaligned when inserted or removed.Type: GrantFiled: December 18, 2014Date of Patent: January 31, 2017Assignee: Intel CorporationInventor: Timothy Wig
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Publication number: 20160181712Abstract: Techniques for manufacturing an add-in card are described. An example of an add-in card in accordance with the described techniques includes a circuit board with contact fingers formed on an outer surface of the circuit board. Each of the contact fingers is configured to make electrical contact with a pin when inserted into a receptacle. The gap between the contact fingers is greater than or equal to a width of the pin. The add-in card also includes a protection mechanism to prevent the pin from being captured between the contact fingers if the add-in card is misaligned when inserted or removed.Type: ApplicationFiled: December 18, 2014Publication date: June 23, 2016Applicant: INTEL CORPORATIONInventor: Timothy Wig
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Publication number: 20140141654Abstract: A Peripheral Component Interconnect Express (PCIe) compliant connector includes a first differential pair of conductors, a second differential pair of conductors, and at least one pair of joined beam ground conductors disposed between the first differential pair of conductors and the second differential pair of conductors. In one embodiment, the ground conductors are joined by an additional conductor. In another embodiment, the ground conductors are joined through a single via. Furthermore, other enhancements, such as joining of AIC ground fingers, may also be implemented. Some of the enhancements potentially reduce crosstalk and suppress resonance for high speed differential links.Type: ApplicationFiled: October 17, 2013Publication date: May 22, 2014Inventors: Timothy WIG, Dennis MILLER
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Publication number: 20140106582Abstract: An electronic device for transmitting data is described herein. In some examples, the electronic device includes a package substrate, and a plurality of integrated circuits to be coupled to the package substrate, at least one integrated circuit comprising a topside connector or an edge connector to be coupled to a cable that is to couple to a cable receptacle.Type: ApplicationFiled: October 16, 2013Publication date: April 17, 2014Inventors: Timothy Wig, Todd Hinck, Sanka Ganesan
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Patent number: 7605671Abstract: Component-less termination for electromagnetic couplers used in high speed/frequency differential signaling is described. In one embodiment, the apparatus includes a first signal line and a second signal line forming a differential pair, a first electromagnetic coupler to provide sampled electromagnetic signals from the first signal line, and a second electromagnetic coupler to provide sampled electromagnetic signals from the second signal line, wherein the first electromagnetic coupler is far end short circuited and wherein the second electromagnetic coupler is far end open circuited. Other embodiments are also described and claimed.Type: GrantFiled: September 26, 2007Date of Patent: October 20, 2009Assignee: Intel CorporationInventors: Tao Liang, Bo Zhang, John Critchlow, Timothy Wig, Larry Tate
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Publication number: 20090079522Abstract: Component-less termination for electromagnetic couplers used in high speed/frequency differential signaling is described. In one embodiment, the apparatus includes a first signal line and a second signal line forming a differential pair, a first electromagnetic coupler to provide sampled electromagnetic signals from the first signal line, and a second electromagnetic coupler to provide sampled electromagnetic signals from the second signal line, wherein the first electromagnetic coupler is far end short circuited and wherein the second electromagnetic coupler is far end open circuited. Other embodiments are also described and claimed.Type: ApplicationFiled: September 26, 2007Publication date: March 26, 2009Inventors: TAO LIANG, Bo Zhang, John Critchlow, Timothy Wig, Larry Tate
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Patent number: 7501586Abstract: A method and apparatus for improving printed circuit board signal layer transitions are described. In one embodiment, the method includes the formation of a first via within a printed circuit board (PCB). A second via is formed concurrently within the PCB. In one embodiment, the second via is positioned proximate the first via to enable electromagnetic coupling between the first and second vias. Following formation of the second via, the first and second vias are connected to provide a series connection between the first and second vias. In one embodiment, the series connection between the first and second vias reduces a stub length with respect to the first via to reduce and potentially eliminate stub resonance for, for example, short signal layer transitions. Other embodiments are described and claimed.Type: GrantFiled: October 29, 2004Date of Patent: March 10, 2009Assignee: Intel CorporationInventors: Timothy Wig, Tao Liang
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Publication number: 20060090933Abstract: A method and apparatus for improving printed circuit board signal layer transitions are described. In one embodiment, the method includes the formation of a first via within a printed circuit board (PCB). A second via is formed concurrently within the PCB. In one embodiment, the second via is positioned proximate the first via to enable electromagnetic coupling between the first and second vias. Following formation of the second via, the first and second vias are connected to provide a series connection between the first and second vias. In one embodiment, the series connection between the first and second vias reduces a stub length with respect to the first via to reduce and potentially eliminate stub resonance for, for example, short signal layer transitions. Other embodiments are described and claimed.Type: ApplicationFiled: October 29, 2004Publication date: May 4, 2006Inventors: Timothy Wig, Tao Liang
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Publication number: 20050025252Abstract: At least two sequences of predetermined reference times are established on respective ones of at least two communication lines. At least some of the reference times of at least one of the sequences occur out-of-phase with at least some of the reference times of another of the sequences. Digital data is encoded onto data signals on one or more communication lines such that a time difference between at least one of the data signals and the nearest one of the reference times on one of the communication lines is smaller than the time difference between the same data signal and the nearest one of the reference times on another one of the communication lines.Type: ApplicationFiled: July 28, 2003Publication date: February 3, 2005Inventors: Larry Tate, Timothy Wig