Patents by Inventor Timour Paltashev

Timour Paltashev has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070030277
    Abstract: A method for processing graphics data packets comprises allocating an entity for the graphics data packet of vertices, triangles, and/or pixels in one or more execution blocks that receives an assignment from a global spreader to process the graphics data packets. A pointer, which points to the allocated entity, communicates a pointer to a data mover, and the data mover loads some graphics data packets into a memory. A number of processing stages may follow such that one or more floating point or integer instructions is executed on the graphics data packets, as controlled by a thread controller. Upon completion of calculations on the graphics data packets, the allocated entity may be deleted and the graphics data packets may be communicated to another execution block or as directed by the global spreader.
    Type: Application
    Filed: August 8, 2005
    Publication date: February 8, 2007
    Inventors: Boris Prokopenko, Timour Paltashev, Derek Gladding, Jeremiah Childs
  • Publication number: 20070030280
    Abstract: A parallel graphics processor having a spreader coupled to a plurality of execution components is disclosed. The spreader maintains status information for each of the plurality of execution components and establishes a priority for each of the plurality of execution blocks to receive a graphics entity to be processed. The priorities are arranged in accordance with the maintained status information and a type of graphics entity to be processed. The spreader communicates a request to a selected execution component to allocate the graphics entity to be processed in its entity descriptor table and copies graphics entity data to the selected execution component. The spreader indexes assignment of the graphics entity in its logical table and subsequently receives indication from the selected instruction execution component that the graphics entity has been processed. Thereafter, graphics images may be presented on a display.
    Type: Application
    Filed: August 8, 2005
    Publication date: February 8, 2007
    Inventors: Timour Paltashev, Boris Prokopenko, Derek Gladding
  • Publication number: 20070030279
    Abstract: A system and method to manage data processing stages of a logical graphics pipeline comprises a number of execution blocks coupled together and to a global spreader that assigns graphics data entities for execution to the execution blocks. Each execution block has an entity descriptor table containing information about an assigned graphics data entity corresponding to allocation of the entity and a current processing stage associated with the entity. Each execution block includes a stage parser configured to establish pointers for the assigned graphics data entity to be processed on a next processing stage. A numerical processing unit is included and configured to execute floating point and integer instructions in association with the assigned graphics data entity. The execution blocks include a data move unit for data loads and moves within the execution block, with the global spreader, and with other execution blocks of the plurality of execution blocks.
    Type: Application
    Filed: August 8, 2005
    Publication date: February 8, 2007
    Inventors: Timour Paltashev, Boris Prokopenko
  • Patent number: 7159003
    Abstract: A system and method for converting two binary digits into redundant sign-digit format. The system comprises a first adder for adding the binary digits together to generate a first result. A second adder adds an input carry from a previous digit to the first result and subtracts a value equal to the radix of the of the binary digits form the first result if the first result is greater than an initial threshold in order to generate an intermediate result. The system further includes a third adder for adding a second input carry from the previous digit to the intermediate result and subtracting the value of the radix from the intermediate result if the intermediate result is greater than a prescribed value such that the addition of the two binary digits are in redundant sign-digit format.
    Type: Grant
    Filed: February 21, 2003
    Date of Patent: January 2, 2007
    Assignee: S3 Graphics Co., Ltd.
    Inventors: Boris Prokopenko, Timour Paltashev, Derek Gladding
  • Patent number: 7158143
    Abstract: A faster algorithm for computing the texture of a pixel is disclosed. A major and minor direction in texel space are determined. Steps in the major direction are set to unity and steps in the minor direction are set to the slope of the anistropy line of the footprint. The end points of the anistropy line in the major direction are then positioned to be on grid in the texture space. The texture is computed for each sample along the anistropy line by computing an interpolation cooefficient for the sample, linearly interpolating two texels based on the cooefficient, weighting the interpolated sample, and accumulating the weighted samples. The result is the texture value to be used for the pixel.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: January 2, 2007
    Assignee: VIA Technologies, Inc.
    Inventors: Boris Prokopenko, Timour Paltashev
  • Patent number: 7146486
    Abstract: A scalar processor that includes a plurality of scalar arithmetic logic units and a special function unit. Each scalar unit performs, in a different time interval, the same operation on a different data item, where each different time interval is one of a plurality of successive, adjacent time intervals. Each unit provides an output data item in the time interval in which the unit performs the operation and provides a processed data item in the last of the successive, adjacent time intervals. The special function unit provides a special function computation for the output data item of a selected one of the scalar units, in the time interval in which the selected scalar unit performs the operation, so as to avoid a conflict in use among the scalar units. A vector processing unit includes an input data buffer, the scalar processor, and an output orthogonal converter.
    Type: Grant
    Filed: January 29, 2003
    Date of Patent: December 5, 2006
    Assignee: S3 Graphics Co., Ltd.
    Inventors: Boris Prokopenko, Timour Paltashev, Derek Gladding
  • Patent number: 7098924
    Abstract: A method and apparatus for obtaining an attribute in homogenous space. After obtaining the vertices of a triangle, the world space coordinates and the attribute of each vertex are transformed to homogeneous coordinates and an attribute in viewer space. Then a set of homogenous coefficients of the triangle is computed based on the viewer space vertex homogeneous coordinates, and the viewer space coordinates of each vertex are projected to coordinates in screen space. Pixels in the screen space that are affected by the projected triangle are determined. For each pixel affected by the triangle, a set of barycentric coefficients in viewer space is computed, based on the homogenous triangle coefficients, and a linear interpolation is performed based on the set of viewer space barycentric coefficients and the viewer space attributes of the triangle vertices to obtain the attribute of the pixel affected by the triangle.
    Type: Grant
    Filed: September 24, 2003
    Date of Patent: August 29, 2006
    Assignee: VIA Technologies, Inc.
    Inventors: Boris Prokopenko, Timour Paltashev, Derek Gladding
  • Publication number: 20060119608
    Abstract: A faster algorithm for computing the texture of a pixel is disclosed. A major and minor direction in texel space are determined. Steps in the major direction are set to unity and steps in the minor direction are set to the slope of the anistropy line of the footprint. The end points of the anistropy line in the major direction are then positioned to be on grid in the texture space. The texture is computed for each sample along the anistropy line by computing an interpolation cooefficient for the sample, linearly interpolating two texels based on the cooefficient, weighting the interpolated sample, and accumulating the weighted samples. The result is the texture value to be used for the pixel.
    Type: Application
    Filed: December 3, 2004
    Publication date: June 8, 2006
    Inventors: Boris Prokopenko, Timour Paltashev
  • Publication number: 20060095735
    Abstract: A system for executing instructions is presented. In some embodiments, among others, the system comprises functional units, local multiplexers, local register files, and a global register file, which are communicatively coupled to each other and arranged to accommodate shortened instruction words in multiple-issue processors. These components are arranged to permit greater access to registers by instructions, thereby permitting reduction of the word length, as compared to conventional very long instruction word (VLIW) processors.
    Type: Application
    Filed: November 1, 2004
    Publication date: May 4, 2006
    Inventors: Boris Prokopenko, Timour Paltashev, Derek Davout Gladding
  • Publication number: 20050134603
    Abstract: A low-cost high-speed programmable rasterizer accepting an input set of functionals representing a triangle, clipping planes and a scissoring box, and producing multiple spans per clock cycle as output. A Loader converts the input set from a general form to a special case form accepted by a set of Edge Generators, the restricted input format accepted by the Edge Generators contributing to their efficient hardware implementation.
    Type: Application
    Filed: December 23, 2003
    Publication date: June 23, 2005
    Applicant: Via Technologies, Inc
    Inventors: Konstantine Iourcha, Boris Prokopenko, Timour Paltashev, Derek Gladding
  • Publication number: 20050093873
    Abstract: One embodiment of the present invention is directed to a graphics system comprising logic for generating a mask that identifies bits within a plurality of bits that are not to be impacted by a subsequent computation. The graphics system further comprises compression logic that is responsive to the mask for generating a compressed bit stream, such that the bits that are not to be impacted by the computation are not included in the compressed bit stream. Another embodiment of the present invention is directed to a graphics system comprising logic for generating a mask identifying positions within a plurality of positions of a bit stream that are to be removed during a compression operation.
    Type: Application
    Filed: April 19, 2004
    Publication date: May 5, 2005
    Inventors: Timour Paltashev, Boris Prokopenko
  • Publication number: 20050093872
    Abstract: One embodiment of the present invention is directed to a method for a computer graphics system comprising compressing a plurality of groups of bits by shifting compressed groups of bits into bit positions that are to be removed during the compression, the logic being responsive to a mask, wherein contents of the mask define variable amounts that the plurality of bits are shifted during the compression. Another embodiment is directed to a method for compressing a plurality of groups of bits to eliminate groups of bits that are to be unaffected by a computation, performing the computation, and thereafter decompressing corresponding data after performing the computation to restore data corresponding to previously eliminated groups of bits.
    Type: Application
    Filed: May 21, 2004
    Publication date: May 5, 2005
    Inventors: Timour Paltashev, Boris Prokopenko
  • Publication number: 20040172517
    Abstract: An orthogonal data converter for converting the components of a sequential vector component flow to a parallel vector component flow. The data converter has an input rotator configured to rotate corresponding vector components of the sequential vector component flow by a prescribed amount, and a bank of register files configured to store the rotated vector components. The converter also has an output rotator configured to rotate the position of the vector components read from the bank of register files by a prescribed amount. A controller of the converter is operative to control the addressing of the bank of register files and the rotating of the vector components. In this regard, the controller is operative to write the vector components to the bank of register files in a prescribed order and read the vector components in a prescribed order to generate the parallel vector component flow.
    Type: Application
    Filed: September 19, 2003
    Publication date: September 2, 2004
    Inventors: Boris Prokopenko, Timour Paltashev
  • Publication number: 20040145589
    Abstract: A method and apparatus for obtaining an attribute of a pixel in homogenous space. After obtaining the vertices of a triangle, the world space coordinates and the attribute of each vertex are transformed to coordinates and an attribute in viewer space. Then a set of homogenous coefficients of each vertex is computed based on the viewer space coordinates, and the viewer space coordinates of each vertex are projected to coordinates in screen space. Pixels in the screen space that are affected by the triangle are determined based on the screen space coordinates. For each pixel affected by the triangle, a set of barycentric coefficients in homogenous space is computed, based on the homogenous coefficients, and a linear interpolation is performed based on the set of homogenous barycentric coefficients and the attributes of the vertices in the viewer space to obtain the attribute in the homogenous space of that pixel.
    Type: Application
    Filed: September 24, 2003
    Publication date: July 29, 2004
    Inventors: Boris Prokopenko, Timour Paltashev, Derek Gladding