Patents by Inventor Tin Poay Chuah
Tin Poay Chuah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220302007Abstract: Disclosed herein are via plug capacitors for incorporation into electronic substrates, and related methods and devices. Exemplary via plug capacitor structures include a capacitive element within a via extending at least partially through an electronic substrate and first and second electrodes coupled to the capacitive element.Type: ApplicationFiled: March 17, 2021Publication date: September 22, 2022Applicant: Intel CorporationInventors: Santosh Gangal, Tin Poay Chuah
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Patent number: 11445608Abstract: An electronic device may include a chassis. The electronic device may include a first electronic component that may include a first substrate and a first interconnect. The electronic device may include a second electronic component that may include a second substrate and a second interconnect. The second substrate may be physically separated from the first substrate. An electrical trace may be coupled to the chassis of the electronic device. The electrical trace may be sized and shaped to interface with the first interconnect of the first electronic component. The electrical trace may be sized and shaped to interface with the second interconnect of the second electronic component. The first electronic component and the second electronic component may be in electrical communication through the electrical trace coupled to the chassis of the electronic device.Type: GrantFiled: June 17, 2020Date of Patent: September 13, 2022Assignee: Intel CorporationInventors: Chee How Lim, Eng Huat Goh, Jon Sern Lim, Khai Ern See, Min Suet Lim, Tin Poay Chuah, Yew San Lim
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Patent number: 11375617Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a first rigid substrate, a second rigid substrate, a flexible substrate comprising a first portion attached to the first rigid substrate, a second portion attached to the second rigid substrate, a middle portion connecting the first portion to the second portion, wherein the middle portion is bent, and metallic traces therethrough, and a component forming a direct interface with the middle portion of the flexible substrate, the component electrically coupled to the metallic traces. In selected examples, the device further includes a casing.Type: GrantFiled: May 29, 2020Date of Patent: June 28, 2022Assignee: Intel CorporationInventors: Tin Poay Chuah, Bok Eng Cheah, Jackson Chung Peng Kong
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Patent number: 11355427Abstract: Techniques and mechanisms to facilitate connectivity between circuit components via a substrate. In an embodiment, a microelectronic device includes a substrate, wherein a recess region extends from the first side of the substrate and only partially toward a second side of the substrate. First input/output (IO) contacts of a first hardware interface are disposed in the recess region. The first IO contacts are variously coupled to each to a respective metallization layer of the substrate, wherein the recess region extends though one or more other metallization layers of the substrate. In another embodiment, the microelectronic device further comprises second IO contacts of a second hardware interface, the second IO contacts to couple the microelectronic device to a printed circuit board.Type: GrantFiled: July 1, 2016Date of Patent: June 7, 2022Assignee: Intel CorporationInventors: Howe Yin Loo, Sujit Sharan, Tin Poay Chuah, Ananth Prabhakumar
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Publication number: 20220174820Abstract: In one embodiment, a system includes a first circuit defining recesses along an edge of the first circuit board, and a second circuit board defining fins extending from at least one outer edge of the second circuit board. The fins of the second circuit board are positioned within the recesses of the second circuit board to connect the circuit boards in a co-planar manner. The fins and recesses may be shaped to provide an interlocking connection of the first and second circuit boards in the co-planar direction.Type: ApplicationFiled: February 14, 2022Publication date: June 2, 2022Applicant: Intel CorporationInventors: Mooi Ling Chang, Tin Poay Chuah, Eng Huat Goh, Min Suet Lim, Twan Sing Loo
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Patent number: 11343906Abstract: The present disclosure generally relates to a scalable computer circuit board having a first power level semiconductor package coupled to at least one base-level voltage regulator module, which is coupled to a plurality of connection receptacles that are configured for connecting with a voltage regulator module positioned on a second level, as a standardized base unit. To scale the base unit, a second power level semiconductor package may be exchanged for the first power level semiconductor package in conjunction with one or more voltage regulator module board being positioned over a corresponding number of base-level voltage regulator modules and coupled to their plurality of connection receptacles.Type: GrantFiled: August 10, 2020Date of Patent: May 24, 2022Assignee: Intel CorporationInventors: Tai Loong Wong, Fern Nee Tan, Tin Poay Chuah, Min Suet Lim, Siang Yeong Tan
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Patent number: 11304299Abstract: A system for board-to-board interconnect is described herein. The system includes a first printed circuit board (PCB) having a first recess along a first edge of the first PCB that exposes a first solder pad on a layer of the first PCB. The system also includes a second PCB having a second recess along a second edge of the second PCB that exposes a second solder pad on a layer of the second PCB. The second recess is complementary to the first recess to allow the first PCB to mate with the second PCB. The first solder pad is aligned with the second solder pad when the first PCB is mated with the second PCB. The system additionally includes an assembly configured to electronically couple the first solder pad with the second solder pad.Type: GrantFiled: August 31, 2020Date of Patent: April 12, 2022Assignee: Intel CorporationInventors: Chee Ling Wong, Wil Choon Song, Khang Choong Yong, Eng Huat Goh, Mohd Muhaiyiddin Bin Abdullah, Tin Poay Chuah
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Publication number: 20220110214Abstract: An apparatus comprising a package comprising a first side to interface with at least one chip; and a second side to interface with a circuit board, the second side opposite to the first side, wherein the second side comprises a non-stepped portion comprising a first plurality of conductive contacts; and a stepped portion that protrudes from the non-stepped portion, the stepped portion comprising a second plurality of conductive contacts.Type: ApplicationFiled: December 14, 2021Publication date: April 7, 2022Applicant: Intel CorporationInventors: Martin M. Chang, Tin Poay Chuah, Eng Huat Goh, Chu Aun Lim, Min Suet Lim
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Publication number: 20220095456Abstract: In one embodiment, a printed circuit board includes a first circuit board portion comprising a set of first conducting layers and one or more plated through hole (PTH) vias formed through the first conducting layers and a second circuit board portion comprising a set of second conducting layers. The second circuit board portion has an area less than an area of the first circuit board portion, and the second circuit board portion is coupled to the first circuit board portion via a laminate layer such that the first and second conducting layers are parallel with one another. The printed circuit board further includes one or more PTH vias formed through the first and second conducting layers in an area of the printed circuit board where the first and second circuit board portions overlap.Type: ApplicationFiled: December 6, 2021Publication date: March 24, 2022Applicant: Intel CorporationInventors: Arumanayagam Rajasekar, Tin Poay Chuah, Sushil Padmanabhan, Aiswarya M. Pious, Navneet Kumar Singh
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Publication number: 20220075410Abstract: According to the present disclosure, a laptop may be provided with a smaller z-height using a motherboard assembly, including a motherboard having a plurality of components coupled thereon, a thermal transfer unit coupled to one or more component on the motherboard and attachment members for holding the motherboard in a lower compartment of a laptop clamshell casing at an inclining position.Type: ApplicationFiled: November 5, 2020Publication date: March 10, 2022Inventors: Min Suet LIM, Chee Chun YEE, Yew San LIM, Jeff KU, Tin Poay CHUAH
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Publication number: 20220078911Abstract: A multilayer printed circuit board including a first printed circuit board portion, including a first inserting connector, including a plurality of contacts for creating a first removable bus connection; a second printed circuit board portion, including a second inserting connector, including a plurality of contacts for creating a second removable bus connection; a third printed circuit board portion, connected between the first printed circuit board portion and to the second printed circuit board portion, wherein a rigidity of the third printed circuit board portion is less than a rigidity of each of the first printed circuit board portion and the second printed circuit board portion; wherein the multilayer printed circuit board is foldable along the third printed circuit board portion and, if so folded, the first printed circuit board portion is arranged on top of the second printed circuit board portion.Type: ApplicationFiled: November 6, 2020Publication date: March 10, 2022Inventors: Tin Poay CHUAH, Min Suet LIM, Chee Chun YEE, Yew San LIM, Eng Huat GOH
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Publication number: 20220066506Abstract: The present disclosure relates to a docking station including a triangular prism shaped body, and a cradle proximal to a top section of the triangular prism shaped body for detachably receiving a mobile device, wherein the cradle may include a plurality of different connection interfaces to provide a selectable connection with a complementary connection interface of the mobile device.Type: ApplicationFiled: November 4, 2020Publication date: March 3, 2022Inventors: Jeff KU, Tin Poay CHUAH, Yew San LIM, Min Suet LIM, Chee Chun YEE
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Publication number: 20220066509Abstract: According to the various examples, a dual display system having a first panel having a first display area, a second panel having a second display area, and a connector assembly, attached to the first and second panels, that is configured to enable the first and second panels to rotate around three-directional axes. The connector assembly includes an elongated member and a hinge assembly, which are configured for attachment to the first and second display panels. The present dual display system may have several functional modalities, including use as a desktop computer, a laptop computer, a tablet, and a panoramic display.Type: ApplicationFiled: November 4, 2020Publication date: March 3, 2022Inventors: Chee Chun YEE, Tin Poay CHUAH, Yew San LIM, Min Suet LIM, Jeff KU
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Publication number: 20220068834Abstract: According to the various aspects, the present device includes a printed circuit board having a top surface and a bottom surface, with a plurality of semiconductor devices coupled to the top surface and a flexible electromagnetic shield wrap conformally positioned over and between the plurality of semiconductor devices and the top surface of the printed circuit board. The flexible electromagnetic shield wrap is conformally positioned by applying a vacuum and is removable after the vacuum seal is broken.Type: ApplicationFiled: November 5, 2020Publication date: March 3, 2022Inventors: Eng Huat GOH, Tin Poay CHUAH, Yew San LIM, Min Suet LIM
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Publication number: 20220015272Abstract: Particular embodiments described herein provide for an electronic device that can be configured to include a radiation shield that includes a zipper.Type: ApplicationFiled: September 22, 2021Publication date: January 13, 2022Applicant: Intel CorporationInventors: Yew San Lim, Jeff Ku, Boon Ping Koh, Min Suet Lim, Tin Poay Chuah
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Publication number: 20210410273Abstract: The present disclosure is directed to a hybrid dielectric interconnect stack for a printed circuit board having a first dielectric layer with a first dielectric constant and a first dielectric loss tangent positioned over an intermediate layer, which includes a first dielectric sublayer with a first sublayer dielectric constant and a first sublayer dielectric loss tangent, an embedded conductive layer, and a second dielectric sublayer with a second sublayer dielectric constant and a second sublayer dielectric loss tangent, in which the embedded conductive layer is positioned between the first and second dielectric sublayers, and a second dielectric layer with a second dielectric constant and a second dielectric loss tangent, in which the intermediate layer is positioned between the first and second dielectric layers.Type: ApplicationFiled: July 6, 2021Publication date: December 30, 2021Inventors: Jackson Chung Peng KONG, Bok Eng CHEAH, Jenny Shio Yin ONG, Seok Ling LIM, Chin Lee KUAN, Tin Poay CHUAH
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Publication number: 20210410341Abstract: Particular embodiments described herein provide for an electronic device that can be configured to include a support structure that includes a radiation shield groove that extends past a surface of the support structure and into the support structure, a radiation source on the substrate, and a radiation shield around the radiation source, where the radiation shield includes a wall secured to the support structure and a groove channel coupling wall that extends past a surface of the support structure and into the radiation shield groove.Type: ApplicationFiled: September 10, 2021Publication date: December 30, 2021Applicant: Intel CorporationInventors: Boon Ping Koh, Twan Sing Loo, Yew San Lim, Tin Poay Chuah
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Publication number: 20210385942Abstract: The present disclosure generally relates to a scalable computer circuit board having a first power level semiconductor package coupled to at least one base-level voltage regulator module, which is coupled to a plurality of connection receptacles that are configured for connecting with a voltage regulator module positioned on a second level, as a standardized base unit. To scale the base unit, a second power level semiconductor package may be exchanged for the first power level semiconductor package in conjunction with one or more voltage regulator module board being positioned over a corresponding number of base-level voltage regulator modules and coupled to their plurality of connection receptacles.Type: ApplicationFiled: August 10, 2020Publication date: December 9, 2021Inventors: Tai Loong Wong, Fern Nee Tan, Tin Poay Chuah, Min Suet Lim, Siang Yeong Tan
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Publication number: 20210385948Abstract: The present disclosure relates to a printed circuit board assembly including a first circuit board including a first footprint, the first circuit board further includes a plurality of first vertical vias extending between a first side and an opposing second side; a second circuit board including a second footprint smaller than the first footprint, the second circuit board further includes a plurality of second vertical vias extending between a subsequent first side and an opposing subsequent second side; an adhesive layer coupling the first side to the subsequent first side; and a plurality of third vertical vias extending through the first side and the subsequent first side.Type: ApplicationFiled: August 25, 2021Publication date: December 9, 2021Inventors: Jackson Chung Peng KONG, Bok Eng CHEAH, Tin Poay CHUAH, Jenny Shio Yin ONG, Seok Ling LIM
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Patent number: 11178768Abstract: Three-dimensional (3-D) volumetric board architectural design provides technical solutions to technical problems facing miniaturization of circuit boards. The 3-D volumetric architecture includes using more of the unused volume in the vertical dimension (e.g., Z-dimension) to increase the utilization of the total circuit board volume. The 3-D volumetric architecture is realized by mounting components on a first PCB and on a second PCB, and inverting and suspending the second PCB above the first PCB. The use of 3-D volumetric board architectural design further enables formation of a shielded FEMIE, providing shielding and improved volumetric use with little or no reduction in system performance or increase in system Z-height.Type: GrantFiled: April 1, 2016Date of Patent: November 16, 2021Assignee: Intel CorporationInventors: Khang Choong Yong, Stephen H. Hall, Tin Poay Chuah, Boon Ping Koh, Eng Huat Goh